first commit

external/patch/atf/atf-sunxi64/add-SRAM-mapping-for-SCPI.patch.disabled

@@ -0,0 +1,29 @@
+From 5ff3a09d64b6b9172d9007e3f77116902b9c2965 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 8 Aug 2016 02:34:27 +0100
+Subject: [PATCH] sunxi: add SRAM regions to EL3 mapping
+
+Currently we only map the MMIO regions for actual peripheral devices
+in EL3. For the SCPI implementation we need access to the SRAM regions
+as well.
+Add a mapping entry that covers all three SRAM regions on the A64.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ plat/sun50iw1p1/aarch64/sunxi_common.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/plat/sun50iw1p1/aarch64/sunxi_common.c b/plat/sun50iw1p1/aarch64/sunxi_common.c
+index a2fa37a39..8ebcd9852 100644
+--- a/plat/sun50iw1p1/aarch64/sunxi_common.c
++++ b/plat/sun50iw1p1/aarch64/sunxi_common.c
+@@ -56,6 +56,9 @@ plat_config_t plat_config;
+  */
+ const mmap_region_t sunxi_mmap[] = {
+ 
++	// SRAM regions
++	{ 0x0010000,			0x0010000,
++		0x0030000,			MT_DEVICE | MT_RW | MT_NS },
+ 	// MMI/O region used by peripherals from 0x100.0000 to 0x200.0000
+ 	{ 0x1000000,			0x1000000,
+ 		0x1000000,			MT_DEVICE | MT_RW | MT_SECURE },

external/patch/atf/atf-sunxi64/enable-a53-errata-workaround.patch.disabled

@@ -0,0 +1,28 @@
+From 3efb52570e581d79f6e451ef88933423a61a9b55 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 27 Mar 2017 21:56:08 +0100
+Subject: [PATCH] Makefile: (re-)enable A53 errata workaround
+
+The --fix-cortex-a53-843418 option to the linker was disabled before to
+also support older toolchains which don't know of this option.
+To not loose the bugfix for more recent toolchains introduce a feature
+check, which enables the option if the linker knows about it.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index f96e2cb37..87c307ded 100644
+--- a/Makefile
++++ b/Makefile
+@@ -234,7 +234,7 @@ CFLAGS			+= 	-nostdinc -pedantic -ffreestanding -Wall	\
+ CFLAGS			+=	-ffunction-sections -fdata-sections
+ LDFLAGS			+=	--fatal-warnings -O1
+ LDFLAGS			+=	--gc-sections
+-#LDFLAGS		+=	--fix-cortex-a53-843419
++LDFLAGS			+=	$(if $(shell $(LD) -v --fix-cortex-a53-843419 > /dev/null 2>&1 && echo 1),--fix-cortex-a53-843419)
+ 
+ 
+ CC			:=	${CROSS_COMPILE}gcc

external/patch/atf/atf-sunxi64/enable-additional-regulators.patch.disabled

@@ -0,0 +1,34 @@
+diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
+index a2ded04..75574b9
+--- a/plat/sun50iw1p1/sunxi_power.c
++++ b/plat/sun50iw1p1/sunxi_power.c
+@@ -229,8 +229,8 @@ static int pmic_setup(const char *dt_name)
+
+ 	/* Enable DC1SW to power PHY, DLDO4 for WiFi and DLDO1 for HDMI */
+ 	ret = sunxi_pmic_read(0x12);
+-	if ((ret & 0xc8) != 0xc8) {
+-		ret = sunxi_pmic_write(0x12, ret | 0xc8);
++	if ((ret & 0xd9) != 0xd9) {
++		ret = sunxi_pmic_write(0x12, ret | 0xd8);
+ 		if (ret < 0) {
+ 			NOTICE("PMIC: error %d enabling DC1SW/DLDO4/DLDO1\n",
+ 			       ret);
+@@ -272,8 +272,17 @@ static int pmic_setup(const char *dt_name)
+ 
+ 		INFO("PMIC: enabled Pinebook display\n");
+ 	}
+- 
++
+ 	sunxi_pmic_write(0x15, 0x1a);	/* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
++	sunxi_pmic_write(0x21, 60);		/* Set DCDC2/CPU voltage to 1.1V */
++	sunxi_pmic_write(0x16, 0x12);	/* DLDO2 = VCC2V5_EDP voltage = 2.5V */
++	sunxi_pmic_write(0x1c, 0xa);	/* FLDO1 = VCC1V2_EDP voltage = 1.2V */
++	sunxi_pmic_write(0x91, 0x1a);	/* GPIO0LDO voltage = 3.3V */
++	sunxi_pmic_write(0x90, 0x3);	/* Enable GPIO0LDO */
++	sunxi_pmic_write(0x30, sunxi_pmic_read(0x30) | BIT(2)); /* Enable USB at Lime64 */
++	ret = sunxi_pmic_read(0x13);
++	/* Enable FLDO1 to power up eDP bridge */
++	ret = sunxi_pmic_write(0x13, ret | 0x4);
+ 
+ 	return 0;
+ }

external/patch/atf/atf-sunxi64/set-rsb-to-nonsec.patch.disabled

@@ -0,0 +1,15 @@
+diff --git a/plat/sun50iw1p1/sunxi_security.c b/plat/sun50iw1p1/sunxi_security.c
+index c0036c12..76d296bd 100644
+--- a/plat/sun50iw1p1/sunxi_security.c
++++ b/plat/sun50iw1p1/sunxi_security.c
+@@ -58,8 +58,9 @@ void sunxi_security_setup(void)
+ 	for (i = 0; i < 6; i++)
+ 		mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
+ 
+-	/* switch RSB to secure */
++	/* switch RSB to secure
+ 	mmio_write_32(SPC_DECPORT_CLR_REG(3), 0x08);
++	*/
+ 	
+ 	/* set CCMU mbus_sec, bus_sec, pll_sec to non-secure */
+ 	mmio_write_32(0x01c20000+0x2f0, 0x7);