3045 lines
76 KiB
Plaintext
3045 lines
76 KiB
Plaintext
/dts-v1/;
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/ {
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interrupt-parent = <0x1>;
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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model = "Orange Pi R1B";
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compatible = "allwinner,h616", "arm,sun50iw9p1";
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aliases {
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serial0 = "/soc@3000000/uart@5000000";
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serial1 = "/soc@3000000/uart@5000400";
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serial2 = "/soc@3000000/uart@5000800";
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serial3 = "/soc@3000000/uart@5000c00";
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serial4 = "/soc@3000000/uart@5001000";
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serial5 = "/soc@3000000/uart@5001400";
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pwm = "/soc@3000000/pwm@300a000";
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pwm0 = "/soc@3000000/pwm0@300a010";
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pwm1 = "/soc@3000000/pwm1@300a011";
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pwm2 = "/soc@3000000/pwm2@300a012";
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pwm3 = "/soc@3000000/pwm3@300a013";
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pwm4 = "/soc@3000000/pwm4@300a014";
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pwm5 = "/soc@3000000/pwm5@300a015";
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ir0 = "/soc@3000000/s_cir@7040000";
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mmc0 = "/soc@3000000/sdmmc@4020000";
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mmc2 = "/soc@3000000/sdmmc@4022000";
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tv0 = "/soc@3000000/tv0@6520000";
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gmac0 = "/soc@3000000/eth@5020000";
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gmac1 = "/soc@3000000/eth@5030000";
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ac200 = "/soc@3000000/ac200";
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nand0 = "/soc@3000000/nand0@4011000";
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ve0 = "/soc@3000000/ve@1c0e000";
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ve1 = "/soc@3000000/ve1@1c0e000";
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disp = "/uboot_disp@1000000";
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lcd0 = "/soc@3000000/lcd0@1c0c000";
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pmu0 = "/soc@3000000/twi@7081400/pmu";
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standby_param = "/soc@3000000/twi@7081400/pmu/standby_param";
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hdmi = "/uboot_hdmi@6000000";
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spi0 = "/soc@3000000/spi@5010000";
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spi1 = "/soc@3000000/spi@5011000";
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twi0 = "/soc@3000000/twi@5002000";
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twi1 = "/soc@3000000/twi@5002400";
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twi2 = "/soc@3000000/twi@5002800";
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twi3 = "/soc@3000000/twi@5002c00";
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twi4 = "/soc@3000000/twi@5003000";
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twi5 = "/soc@3000000/twi@7081400";
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};
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reserved-memory {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges;
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bl31 {
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reg = <0x0 0x48000000 0x0 0x1000000>;
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};
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};
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firmware {
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android {
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compatible = "android,firmware";
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boot_devices = "soc@3000000/4020000.sdmmc,soc@3000000/4022000.sdmmc,soc@3000000";
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vbmeta {
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compatible = "android,vbmeta";
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parts = "vbmeta,vbmeta_system,vbmeta_vendor,boot";
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};
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};
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <0x2 0x15>;
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operating-points-v2 = <0x3>;
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cpu-idle-states = <0x4>;
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dynamic-power-coefficient = <0xca>;
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#cooling-cells = <0x2>;
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cpu-supply = <0x5>;
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phandle = <0x76>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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clocks = <0x2 0x15>;
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operating-points-v2 = <0x3>;
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cpu-idle-states = <0x4>;
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dynamic-power-coefficient = <0xca>;
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#cooling-cells = <0x2>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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clocks = <0x2 0x15>;
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operating-points-v2 = <0x3>;
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cpu-idle-states = <0x4>;
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dynamic-power-coefficient = <0xca>;
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#cooling-cells = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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clocks = <0x2 0x15>;
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operating-points-v2 = <0x3>;
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cpu-idle-states = <0x4>;
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dynamic-power-coefficient = <0xca>;
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#cooling-cells = <0x2>;
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};
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idle-states {
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entry-method = "psci";
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cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x10000>;
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entry-latency-us = <0x2e>;
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exit-latency-us = <0x3b>;
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min-residency-us = <0xdf2>;
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phandle = <0x4>;
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};
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};
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};
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cpu-opp-table {
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compatible = "allwinner,sun50i-operating-points";
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nvmem-cells = <0x6>;
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nvmem-cell-names = "speed";
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opp-shared;
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phandle = <0x3>;
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opp@480000000 {
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opp-hz = <0x0 0x1c9c3800>;
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opp-microvolt-a0 = <0xdbba0>;
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opp-microvolt-a1 = <0xdbba0>;
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opp-microvolt-a2 = <0xdbba0>;
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opp-microvolt-a3 = <0xdbba0>;
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opp-microvolt-a4 = <0xdbba0>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0x1f>;
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};
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opp@600000000 {
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opp-hz = <0x0 0x23c34600>;
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opp-microvolt-a1 = <0xdbba0>;
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opp-microvolt-a4 = <0xdbba0>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0x12>;
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};
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opp@720000000 {
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opp-hz = <0x0 0x2aea5400>;
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opp-microvolt-a0 = <0xdbba0>;
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opp-microvolt-a2 = <0xdbba0>;
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opp-microvolt-a3 = <0xdbba0>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0xd>;
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};
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opp@792000000 {
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opp-hz = <0x0 0x2f34f600>;
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opp-microvolt-a1 = <0xdbba0>;
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opp-microvolt-a4 = <0xe57e0>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0x12>;
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};
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opp@936000000 {
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opp-hz = <0x0 0x37ca3a00>;
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opp-microvolt-a0 = <0xdbba0>;
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opp-microvolt-a2 = <0xdbba0>;
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opp-microvolt-a3 = <0xdbba0>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0xd>;
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};
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opp@1008000000 {
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opp-hz = <0x0 0x3c14dc00>;
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opp-microvolt-a0 = <0xe7ef0>;
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opp-microvolt-a1 = <0xe57e0>;
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opp-microvolt-a2 = <0xe7ef0>;
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opp-microvolt-a3 = <0xe7ef0>;
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opp-microvolt-a4 = <0xf9060>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0x1f>;
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};
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opp@1104000000 {
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opp-hz = <0x0 0x41cdb400>;
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opp-microvolt-a0 = <0xf4240>;
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opp-microvolt-a2 = <0xf4240>;
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opp-microvolt-a3 = <0xf4240>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0xd>;
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};
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opp@1200000000 {
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opp-hz = <0x0 0x47868c00>;
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opp-microvolt-a0 = <0x100590>;
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opp-microvolt-a1 = <0xf9060>;
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opp-microvolt-a2 = <0x100590>;
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opp-microvolt-a3 = <0x100590>;
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opp-microvolt-a4 = <0x10c8e0>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0x1f>;
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};
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opp@1320000000 {
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opp-hz = <0x0 0x4ead9a00>;
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opp-microvolt-a0 = <0x10c8e0>;
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opp-microvolt-a2 = <0x10c8e0>;
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opp-microvolt-a3 = <0x10c8e0>;
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opp-microvolt-a4 = <0x111700>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0x1d>;
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};
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opp@1416000000 {
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opp-hz = <0x0 0x54667200>;
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opp-microvolt-a0 = <0x118c30>;
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opp-microvolt-a2 = <0x118c30>;
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opp-microvolt-a3 = <0xb10080>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0xd>;
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};
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opp@1512000000 {
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opp-hz = <0x0 0x5a1f4a00>;
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opp-microvolt-a1 = <0x10c8e0>;
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opp-microvolt-a3 = <0x10c8e0>;
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clock-latency-ns = <0x3b9b0>;
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opp-supported-hw = <0xa>;
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};
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};
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dump-reg@20000 {
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compatible = "allwinner,sunxi-dump-reg";
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reg = <0x0 0x20000 0x0 0x4>;
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phandle = <0x78>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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internal-osc-clk {
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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clock-frequency = <0xf42400>;
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clock-accuracy = <0x11e1a300>;
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clock-output-names = "iosc";
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phandle = <0xc>;
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};
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dcxo24M-clk {
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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clock-frequency = <0x16e3600>;
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clock-output-names = "dcxo24M";
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phandle = <0xa>;
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};
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osc32k-clk {
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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clock-frequency = <0x8000>;
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clock-output-names = "osc32k";
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phandle = <0xb>;
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};
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interrupt-controller@3021000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <0x3>;
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#address-cells = <0x0>;
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interrupt-controller;
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reg = <0x0 0x3021000 0x0 0x1000 0x0 0x3022000 0x0 0x2000 0x0 0x3024000 0x0 0x2000 0x0 0x3026000 0x0 0x2000>;
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interrupts = <0x1 0x9 0xf04>;
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interrupt-parent = <0x7>;
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phandle = <0x7>;
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};
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interrupt-controller@0 {
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compatible = "allwinner,sunxi-wakeupgen";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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interrupt-parent = <0x7>;
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phandle = <0x1>;
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};
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timer_arch {
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compatible = "arm,armv8-timer";
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interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>;
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clock-frequency = <0x16e3600>;
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interrupt-parent = <0x7>;
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arm,no-tick-in-suspend;
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};
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pio-18 {
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compatible = "regulator-fixed";
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regulator-name = "pio-18";
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x1b7740>;
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phandle = <0x17>;
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};
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pio-33 {
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compatible = "regulator-fixed";
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regulator-name = "pio-33";
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regulator-min-microvolt = <0x325aa0>;
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regulator-max-microvolt = <0x325aa0>;
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phandle = <0x18>;
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};
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dram {
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phandle = <0x79>;
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};
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soc@3000000 {
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compatible = "simple-bus";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges;
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phandle = <0x7a>;
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disp@1000000 {
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compatible = "allwinner,sunxi-disp";
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reg = <0x0 0x1000000 0x0 0x1400000 0x0 0x6510000 0x0 0x200 0x0 0x6511000 0x0 0x1000 0x0 0x6512000 0x0 0x1000 0x0 0x6515000 0x0 0x1000 0x0 0x6516000 0x0 0x1000>;
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interrupts = <0x0 0x58 0x4 0x0 0x40 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4>;
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clocks = <0x2 0x1d 0x2 0x1d 0x2 0x1e 0x2 0x1e 0x2 0x7b 0x2 0x7c 0x2 0x7f 0x2 0x80 0x2 0x7d 0x2 0x7e 0x2 0x81 0x2 0x82 0x2 0x7a 0x2 0x7a 0x2 0x7a 0x2 0x7a>;
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clock-names = "clk_de0", "clk_de1", "clk_bus_de0", "clk_bus_de1", "clk_tcon0", "clk_tcon1", "clk_tcon2", "clk_tcon3", "clk_bus_tcon0", "clk_bus_tcon1", "clk_bus_tcon2", "clk_bus_tcon3", "clk_bus_dpss_top0", "clk_bus_dpss_top1", "clk_bus_dpss_top2", "clk_bus_dpss_top3";
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resets = <0x2 0x1 0x2 0x1 0x2 0x39 0x2 0x3a 0x2 0x3b 0x2 0x3c 0x2 0x3d 0x2 0x3d 0x2 0x38 0x2 0x38 0x2 0x38 0x2 0x38>;
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reset-names = "rst_bus_de0", "rst_bus_de1", "rst_bus_tcon0", "rst_bus_tcon1", "rst_bus_tcon2", "rst_bus_tcon3", "rst_bus_lvds0", "rst_bus_lvds1", "rst_bus_dpss_top0", "rst_bus_dpss_top1", "rst_bus_dpss_top2", "rst_bus_dpss_top3";
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assigned-clocks = <0x2 0x7f>;
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assigned-clock-parents = <0x2 0xd>;
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assigned-clock-rates = <0x0>;
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iommus = <0x8 0x0 0x0>;
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boot_disp = <0x0>;
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fb_base = <0x0>;
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disp_init_enable = <0x1>;
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disp_mode = <0x0>;
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screen0_output_type = <0x3>;
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screen0_output_mode = <0xa>;
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screen0_output_format = <0x0>;
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screen0_output_bits = <0x0>;
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screen0_output_eotf = <0x4>;
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screen0_output_cs = <0x101>;
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screen0_output_dvi_hdmi = <0x2>;
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screen0_output_range = <0x2>;
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screen0_output_scan = <0x0>;
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screen0_output_aspect_ratio = <0x8>;
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screen1_output_type = <0x2>;
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screen1_output_mode = <0xb>;
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screen1_output_format = <0x1>;
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screen1_output_bits = <0x0>;
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screen1_output_eotf = <0x4>;
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screen1_output_cs = <0x104>;
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screen1_output_dvi_hdmi = <0x0>;
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screen1_output_range = <0x2>;
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screen1_output_scan = <0x0>;
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screen1_output_aspect_ratio = <0x8>;
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dev0_output_type = <0x4>;
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dev0_output_mode = <0xa>;
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dev0_screen_id = <0x0>;
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dev0_do_hpd = <0x1>;
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dev1_output_type = <0x2>;
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dev1_output_mode = <0xb>;
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dev1_screen_id = <0x1>;
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dev1_do_hpd = <0x1>;
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dev2_output_type = <0x0>;
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def_output_dev = <0x0>;
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hdmi_mode_check = <0x1>;
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fb0_format = <0x0>;
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fb0_width = <0x0>;
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fb0_height = <0x0>;
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fb1_format = <0x0>;
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fb1_width = <0x0>;
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fb1_height = <0x0>;
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chn_cfg_mode = <0x1>;
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disp_para_zone = <0x1>;
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phandle = <0x7b>;
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};
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ve@1c0e000 {
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compatible = "allwinner,sunxi-cedar-ve";
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reg = <0x0 0x1c0e000 0x0 0x1000 0x0 0x3000000 0x0 0x10 0x0 0x3001000 0x0 0x1000>;
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interrupts = <0x0 0x5d 0x4>;
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clocks = <0x2 0x29 0x2 0x28 0x2 0x33>;
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clock-names = "bus_ve", "ve", "mbus_ve";
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resets = <0x2 0x6>;
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iommus = <0x8 0x3 0x1>;
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phandle = <0x7c>;
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};
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ve1@1c0e000 {
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compatible = "allwinner,sunxi-cedar-ve";
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iommus = <0x8 0x2 0x1>;
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phandle = <0x7d>;
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};
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g2d@1480000 {
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compatible = "allwinner,sunxi-g2d";
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reg = <0x0 0x1480000 0x0 0x3ffff>;
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interrupts = <0x0 0x5a 0x4>;
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clocks = <0x2 0x22 0x2 0x21 0x2 0x38>;
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clock-names = "bus", "g2d", "mbus_g2d";
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resets = <0x2 0x3>;
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iommus = <0x8 0x6 0x1>;
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phandle = <0x7e>;
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};
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deinterlace@1420000 {
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|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-deinterlace";
|
|
reg = <0x0 0x1420000 0x0 0x40000>;
|
|
interrupts = <0x0 0x59 0x4>;
|
|
iommus = <0x8 0x1 0x1>;
|
|
status = "okay";
|
|
clocks = <0x2 0x1f 0x2 0x20 0x2 0x5>;
|
|
clock-names = "clk_di", "clk_bus_di", "pll_periph";
|
|
resets = <0x2 0x2>;
|
|
reset-names = "rst_bus_di";
|
|
assigned-clocks = <0x2 0x1f>;
|
|
assigned-clock-parents = <0x2 0x5>;
|
|
assigned-clock-rates = <0x11e1a300>;
|
|
phandle = <0x7f>;
|
|
};
|
|
|
|
gpu@1800000 {
|
|
device_type = "gpu";
|
|
compatible = "arm,mali-midgard";
|
|
reg = <0x0 0x1800000 0x0 0x10000>;
|
|
interrupts = <0x0 0x5f 0x4 0x0 0x60 0x4 0x0 0x61 0x4>;
|
|
interrupt-names = "JOB", "MMU", "GPU";
|
|
clocks = <0x2 0x8 0x2 0x23 0x2 0x24 0x2 0x25>;
|
|
clock-names = "clk_parent", "clk_mali", "clk_bak", "clk_bus";
|
|
resets = <0x2 0x4>;
|
|
#cooling-cells = <0x2>;
|
|
gpu_idle = <0x1>;
|
|
dvfs_status = <0x1>;
|
|
operating-points = <0x927c0 0xe7ef0 0x8ca00 0xe7ef0 0x83d60 0xe7ef0 0x7b0c0 0xe7ef0 0x6f540 0xe7ef0 0x668a0 0xe7ef0 0x5dc00 0xe7ef0 0x57e40 0xe7ef0 0x52080 0xe7ef0 0x4ab50 0xe7ef0>;
|
|
phandle = <0x77>;
|
|
|
|
ipa_dvfs {
|
|
compatible = "arm,mali-simple-power-model";
|
|
static-coefficient = <0x4268>;
|
|
dynamic-coefficient = <0x2ee>;
|
|
ts = <0x3e2da 0x2568 0xffffff98 0x4>;
|
|
thermal-zone = "gpu_thermal_zone";
|
|
ss-coefficient = <0x24>;
|
|
ff-coefficient = <0x123>;
|
|
phandle = <0x80>;
|
|
};
|
|
};
|
|
|
|
lcd0@1c0c000 {
|
|
compatible = "allwinner,sunxi-lcd0";
|
|
reg = <0x0 0x1c0c000 0x0 0x0>;
|
|
pinctrl-names = "active", "sleep";
|
|
lcd_used = <0x0>;
|
|
lcd_driver_name = "default_lcd";
|
|
lcd_backlight = <0x32>;
|
|
lcd_if = <0x0>;
|
|
lcd_x = <0x500>;
|
|
lcd_y = <0x2d0>;
|
|
lcd_width = <0x96>;
|
|
lcd_height = <0x5e>;
|
|
lcd_dclk_freq = <0x46>;
|
|
lcd_pwm_used = <0x0>;
|
|
lcd_pwm_ch = <0x0>;
|
|
lcd_pwm_freq = <0xc350>;
|
|
lcd_pwm_pol = <0x0>;
|
|
lcd_pwm_max_limit = <0xff>;
|
|
lcd_hbp = <0x14>;
|
|
lcd_ht = <0x58a>;
|
|
lcd_hspw = <0xa>;
|
|
lcd_vbp = <0xa>;
|
|
lcd_vt = <0x32e>;
|
|
lcd_vspw = <0x5>;
|
|
lcd_lvds_if = <0x0>;
|
|
lcd_lvds_colordepth = <0x0>;
|
|
lcd_lvds_mode = <0x0>;
|
|
lcd_frm = <0x0>;
|
|
lcd_hv_clk_phase = <0x0>;
|
|
lcd_hv_sync_polarity = <0x0>;
|
|
lcd_gamma_en = <0x0>;
|
|
lcd_bright_curve_en = <0x0>;
|
|
lcd_cmap_en = <0x0>;
|
|
deu_mode = <0x0>;
|
|
lcdgamma4iep = <0x16>;
|
|
smart_color = <0x5a>;
|
|
lcd_pin_power = "bldo1";
|
|
lcd_power = "dc1sw";
|
|
phandle = <0x81>;
|
|
};
|
|
|
|
tv0@6520000 {
|
|
compatible = "allwinner,sunxi-tv";
|
|
reg = <0x0 0x6520000 0x0 0x100 0x0 0x6524000 0x0 0x3fc>;
|
|
clocks = <0x2 0x85 0x2 0x83 0x2 0x84>;
|
|
clock-names = "clk_bus_tve_top", "clk_tve", "clk_bus_tve";
|
|
resets = <0x2 0x3e 0x2 0x3f>;
|
|
reset-names = "rst_bus_tve_top", "rst_bus_tve";
|
|
assigned-clocks = <0x2 0x83>;
|
|
assigned-clock-parents = <0x2 0xb>;
|
|
nvmem-cells = <0x9>;
|
|
nvmem-cell-names = "tvout";
|
|
device_type = "tv0";
|
|
pinctrl-names = "active", "sleep";
|
|
status = "disabled";
|
|
interface = <0x1>;
|
|
dac_type0 = <0x0>;
|
|
dac_src0 = <0x0>;
|
|
phandle = <0x82>;
|
|
};
|
|
|
|
ccu@3001000 {
|
|
compatible = "allwinner,sun50iw9-ccu";
|
|
reg = <0x0 0x3001000 0x0 0x1000>;
|
|
clocks = <0xa 0xb 0xc>;
|
|
clock-names = "hosc", "losc", "iosc";
|
|
#clock-cells = <0x1>;
|
|
#reset-cells = <0x1>;
|
|
phandle = <0x2>;
|
|
};
|
|
|
|
rtc_ccu@7000000 {
|
|
compatible = "allwinner,sun50iw9-rtc-ccu";
|
|
reg = <0x0 0x7000000 0x0 0x400>;
|
|
#clock-cells = <0x1>;
|
|
clocks = <0xb>;
|
|
clock-names = "losc";
|
|
#reset-cells = <0x1>;
|
|
phandle = <0xe>;
|
|
};
|
|
|
|
rtc@7000000 {
|
|
compatible = "allwinner,rtc-v200";
|
|
device_type = "rtc";
|
|
wakeup-source;
|
|
reg = <0x0 0x7000000 0x0 0x200>;
|
|
interrupts = <0x0 0x68 0x4>;
|
|
clocks = <0xd 0x9 0xe 0x0>;
|
|
clock-names = "r-ahb-rtc", "rtc-1k";
|
|
gpr_cur_pos = <0x6>;
|
|
phandle = <0x83>;
|
|
};
|
|
|
|
r_ccu@7010000 {
|
|
compatible = "allwinner,sun50iw9-r-ccu";
|
|
reg = <0x0 0x7010000 0x0 0x300>;
|
|
clocks = <0xa 0xb 0xc 0x2 0x4>;
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
#clock-cells = <0x1>;
|
|
#reset-cells = <0x1>;
|
|
phandle = <0xd>;
|
|
};
|
|
|
|
dma-controller@3002000 {
|
|
compatible = "allwinner,sun50iw9-dma";
|
|
reg = <0x0 0x3002000 0x0 0x1000>;
|
|
interrupts = <0x0 0x2a 0x4>;
|
|
clocks = <0x2 0x2a 0x2 0x32>;
|
|
clock-names = "bus", "mbus";
|
|
dma-channels = <0x10>;
|
|
dma-requests = <0x31>;
|
|
resets = <0x2 0x7>;
|
|
#dma-cells = <0x1>;
|
|
phandle = <0x35>;
|
|
};
|
|
|
|
sram_ctrl@3000000 {
|
|
compatible = "allwinner,sram_ctrl";
|
|
reg = <0x0 0x3000000 0x0 0x16c>;
|
|
phandle = <0x84>;
|
|
|
|
soc_ver {
|
|
offset = <0x24>;
|
|
mask = <0x7>;
|
|
shift = <0x0>;
|
|
};
|
|
|
|
soc_id {
|
|
offset = <0x200>;
|
|
mask = <0x1>;
|
|
shift = <0x16>;
|
|
};
|
|
|
|
soc_bin {
|
|
offset = <0x0>;
|
|
mask = <0x3ff>;
|
|
shift = <0x0>;
|
|
};
|
|
};
|
|
|
|
sid@3006000 {
|
|
compatible = "allwinner,sun50iw9p1-sid", "allwinner,sunxi-sid";
|
|
reg = <0x0 0x3006000 0x0 0x1000>;
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x1>;
|
|
|
|
speed@00 {
|
|
reg = <0x0 0x2>;
|
|
phandle = <0x6>;
|
|
};
|
|
|
|
calib@14 {
|
|
reg = <0x14 0x8>;
|
|
phandle = <0x48>;
|
|
};
|
|
|
|
tvout@2e {
|
|
reg = <0x2c 0x8>;
|
|
phandle = <0x9>;
|
|
};
|
|
|
|
i-cpu@28 {
|
|
reg = <0x28 0x2>;
|
|
phandle = <0x85>;
|
|
};
|
|
|
|
secure_status {
|
|
reg = <0x0 0x0>;
|
|
offset = <0xa0>;
|
|
size = <0x4>;
|
|
};
|
|
|
|
chipid {
|
|
reg = <0x0 0x0>;
|
|
offset = <0x200>;
|
|
size = <0x10>;
|
|
};
|
|
|
|
rotpk {
|
|
reg = <0x0 0x0>;
|
|
offset = <0x270>;
|
|
size = <0x20>;
|
|
};
|
|
};
|
|
|
|
ce@1904000 {
|
|
compatible = "allwinner,sunxi-ce";
|
|
device_name = "ce";
|
|
reg = <0x0 0x1904000 0x0 0xa0 0x0 0x1904800 0x0 0xa0>;
|
|
interrupts = <0x0 0x5b 0x1 0x0 0x5c 0x1>;
|
|
clock-frequency = <0x11e1a300>;
|
|
clocks = <0x2 0x27 0x2 0x26 0x2 0x34 0x2 0x5>;
|
|
clock-names = "bus_ce", "ce_clk", "mbus_ce", "pll_periph0_2x";
|
|
resets = <0x2 0x5>;
|
|
phandle = <0x86>;
|
|
};
|
|
|
|
timer@3009000 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
device_type = "soc_timer";
|
|
reg = <0x0 0x3009000 0x0 0x400>;
|
|
interrupt-parent = <0x7>;
|
|
interrupts = <0x0 0x30 0x4>;
|
|
clocks = <0xa>;
|
|
phandle = <0x87>;
|
|
};
|
|
|
|
watchdog@30090a0 {
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
reg = <0x0 0x30090a0 0x0 0x20>;
|
|
interrupts = <0x0 0x32 0x4>;
|
|
phandle = <0x88>;
|
|
};
|
|
|
|
pwm@300a000 {
|
|
compatible = "allwinner,sunxi-pwm-v100";
|
|
reg = <0x0 0x300a000 0x0 0x400>;
|
|
clocks = <0x2 0x2f>;
|
|
resets = <0x2 0xb>;
|
|
pwm-number = <0x6>;
|
|
pwm-base = <0x0>;
|
|
sunxi-pwms = <0xf 0x10 0x11 0x12 0x13 0x14>;
|
|
phandle = <0x89>;
|
|
};
|
|
|
|
pwm0@300a010 {
|
|
compatible = "allwinner,sunxi-pwm0";
|
|
reg = <0x0 0x300a010 0x0 0x4>;
|
|
reg_base = <0x300a000>;
|
|
phandle = <0xf>;
|
|
};
|
|
|
|
pwm1@300a011 {
|
|
compatible = "allwinner,sunxi-pwm1";
|
|
reg = <0x0 0x300a011 0x0 0x4>;
|
|
reg_base = <0x300a000>;
|
|
phandle = <0x10>;
|
|
};
|
|
|
|
pwm2@300a012 {
|
|
compatible = "allwinner,sunxi-pwm2";
|
|
reg = <0x0 0x300a012 0x0 0x4>;
|
|
reg_base = <0x300a000>;
|
|
phandle = <0x11>;
|
|
};
|
|
|
|
pwm3@300a013 {
|
|
compatible = "allwinner,sunxi-pwm3";
|
|
reg = <0x0 0x300a013 0x0 0x4>;
|
|
reg_base = <0x300a000>;
|
|
phandle = <0x12>;
|
|
};
|
|
|
|
pwm4@300a014 {
|
|
compatible = "allwinner,sunxi-pwm4";
|
|
reg = <0x0 0x300a014 0x0 0x4>;
|
|
reg_base = <0x300a000>;
|
|
phandle = <0x13>;
|
|
};
|
|
|
|
pwm5@300a015 {
|
|
compatible = "allwinner,sunxi-pwm5";
|
|
reg = <0x0 0x300a015 0x0 0x4>;
|
|
reg_base = <0x300a000>;
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <0x15>;
|
|
pinctrl-1 = <0x16>;
|
|
status = "okay";
|
|
phandle = <0x14>;
|
|
};
|
|
|
|
ac200 {
|
|
compatible = "allwinner,sunxi-ac200";
|
|
status = "okay";
|
|
tv_used = <0x1>;
|
|
tv_twi_used = <0x1>;
|
|
tv_twi_id = <0x3>;
|
|
tv_twi_addr = <0x10>;
|
|
tv_pwm_ch = <0x5>;
|
|
phandle = <0x8a>;
|
|
};
|
|
|
|
pinctrl@300b000 {
|
|
compatible = "allwinner,sun50iw9-pinctrl";
|
|
reg = <0x0 0x300b000 0x0 0x400>;
|
|
interrupts = <0x0 0x33 0x4 0x0 0x34 0x4 0x0 0x35 0x4 0x0 0x2b 0x4 0x0 0x36 0x4 0x0 0x37 0x4 0x0 0x38 0x4 0x0 0x39 0x4>;
|
|
clocks = <0x2 0x1a 0xa 0xb>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
#gpio-cells = <0x3>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x3>;
|
|
vcc-pf-supply = <0x17>;
|
|
vcc-pfo-supply = <0x18>;
|
|
vcc-pg-supply = <0x17>;
|
|
phandle = <0x23>;
|
|
|
|
uart0-ph-pins {
|
|
pins = "PH0", "PH1";
|
|
function = "uart0";
|
|
bias-pull-up;
|
|
phandle = <0x29>;
|
|
};
|
|
|
|
uart0-ph-sleep {
|
|
pins = "PH0", "PH1";
|
|
function = "gpio_in";
|
|
phandle = <0x2a>;
|
|
};
|
|
|
|
sdc0@0 {
|
|
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
|
function = "sdc0";
|
|
drive-strength = <0x1e>;
|
|
bias-pull-up;
|
|
power-source = <0xce4>;
|
|
allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
|
allwinner,function = "sdc0";
|
|
allwinner,muxsel = <0x2>;
|
|
allwinner,drive = <0x3>;
|
|
allwinner,pull = <0x1>;
|
|
phandle = <0x1e>;
|
|
};
|
|
|
|
sdc0@1 {
|
|
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
|
function = "sdc0";
|
|
drive-strength = <0x1e>;
|
|
bias-pull-up;
|
|
power-source = <0x708>;
|
|
phandle = <0x1f>;
|
|
};
|
|
|
|
sdc0@2 {
|
|
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
|
function = "gpio_in";
|
|
phandle = <0x20>;
|
|
};
|
|
|
|
sdc0@3 {
|
|
pins = "PF2", "PF4";
|
|
function = "uart0";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x21>;
|
|
};
|
|
|
|
sdc0@4 {
|
|
pins = "PF0", "PF1", "PF3", "PF5";
|
|
function = "jtag";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x22>;
|
|
};
|
|
|
|
sdc1@0 {
|
|
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
|
|
function = "sdc1";
|
|
drive-strength = <0x1e>;
|
|
bias-pull-up;
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
sdc1@1 {
|
|
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
|
|
function = "gpio_in";
|
|
bias-pull-up;
|
|
phandle = <0x25>;
|
|
};
|
|
|
|
sdc2@0 {
|
|
pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC13", "PC14", "PC15", "PC16";
|
|
function = "sdc2";
|
|
drive-strength = <0x1e>;
|
|
bias-pull-up;
|
|
allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC13", "PC14", "PC15", "PC16";
|
|
allwinner,function = "sdc2";
|
|
allwinner,muxsel = <0x3>;
|
|
allwinner,drive = <0x3>;
|
|
allwinner,pull = <0x1>;
|
|
phandle = <0x19>;
|
|
};
|
|
|
|
sdc2@1 {
|
|
pins = "PC0", "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC13", "PC14", "PC15", "PC16";
|
|
function = "gpio_in";
|
|
bias-pull-up;
|
|
phandle = <0x1b>;
|
|
};
|
|
|
|
sdc2@2 {
|
|
allwinner,pins = "PC0";
|
|
allwinner,function = "sdc2";
|
|
drive-strength = <0x1e>;
|
|
bias-pull-down;
|
|
allwinner,muxsel = <0x3>;
|
|
allwinner,drive = <0x3>;
|
|
allwinner,pull = <0x2>;
|
|
phandle = <0x1a>;
|
|
};
|
|
|
|
nand0@0 {
|
|
pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
|
|
function = "nand0";
|
|
drive-strength = <0x28>;
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
nand0@1 {
|
|
pins = "PC4", "PC6", "PC3", "PC7";
|
|
function = "nand0";
|
|
drive-strength = <0x28>;
|
|
bias-pull-up;
|
|
phandle = <0x27>;
|
|
};
|
|
|
|
nand0@2 {
|
|
pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
|
|
function = "gpio_in";
|
|
phandle = <0x28>;
|
|
};
|
|
|
|
uart1-ph-pins {
|
|
pins = "PG6", "PG7", "PG8", "PG9";
|
|
function = "uart1";
|
|
phandle = <0x2b>;
|
|
};
|
|
|
|
uart1-ph-sleep {
|
|
pins = "PG6", "PG7", "PG8", "PG9";
|
|
function = "gpio_in";
|
|
phandle = <0x2c>;
|
|
};
|
|
|
|
uart2-ph-pins {
|
|
pins = "PH5", "PH6";
|
|
function = "uart2";
|
|
phandle = <0x2d>;
|
|
};
|
|
|
|
uart2-ph-sleep {
|
|
pins = "PH5", "PH6";
|
|
function = "gpio_in";
|
|
phandle = <0x2e>;
|
|
};
|
|
|
|
uart3-ph-pins {
|
|
pins = "PI9", "PI10";
|
|
function = "uart3";
|
|
phandle = <0x2f>;
|
|
};
|
|
|
|
uart3-ph-sleep {
|
|
pins = "PI9", "PI10";
|
|
function = "gpio_in";
|
|
phandle = <0x30>;
|
|
};
|
|
|
|
uart4-ph-pins {
|
|
pins = "PI13", "PI14";
|
|
function = "uart4";
|
|
phandle = <0x31>;
|
|
};
|
|
|
|
uart4-ph-sleep {
|
|
pins = "PI13", "PI14";
|
|
function = "gpio_in";
|
|
phandle = <0x32>;
|
|
};
|
|
|
|
uart5-ph-pins {
|
|
pins = "PH2", "PH3";
|
|
function = "uart5";
|
|
phandle = <0x33>;
|
|
};
|
|
|
|
uart5-ph-sleep {
|
|
pins = "PH2", "PH3";
|
|
function = "gpio_in";
|
|
phandle = <0x34>;
|
|
};
|
|
|
|
s_cir0@0 {
|
|
pins = "PH10";
|
|
function = "ir";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x64>;
|
|
};
|
|
|
|
s_cir0@1 {
|
|
pins = "PH10";
|
|
function = "gpio_in";
|
|
phandle = <0x65>;
|
|
};
|
|
|
|
twi0@0 {
|
|
pins = "PI5", "PI6";
|
|
function = "twi0";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x36>;
|
|
};
|
|
|
|
twi0@1 {
|
|
pins = "PI5", "PI6";
|
|
function = "gpio_in";
|
|
phandle = <0x37>;
|
|
};
|
|
|
|
twi1@0 {
|
|
pins = "PH0", "PH1";
|
|
function = "twi1";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x38>;
|
|
};
|
|
|
|
twi1@1 {
|
|
pins = "PH0", "PH1";
|
|
function = "gpio_in";
|
|
phandle = <0x39>;
|
|
};
|
|
|
|
twi2@0 {
|
|
pins = "PH2", "PH3";
|
|
function = "twi2";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x3a>;
|
|
};
|
|
|
|
twi2@1 {
|
|
pins = "PH2", "PH3";
|
|
function = "gpio_in";
|
|
phandle = <0x3b>;
|
|
};
|
|
|
|
twi3@0 {
|
|
pins = "PH4", "PH5";
|
|
function = "twi3";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x3c>;
|
|
};
|
|
|
|
twi3@1 {
|
|
pins = "PH4", "PH5";
|
|
function = "gpio_in";
|
|
phandle = <0x3d>;
|
|
};
|
|
|
|
twi4@0 {
|
|
pins = "PH6", "PH7";
|
|
function = "twi4";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x3e>;
|
|
};
|
|
|
|
twi4@1 {
|
|
pins = "PH6", "PH7";
|
|
function = "gpio_in";
|
|
phandle = <0x3f>;
|
|
};
|
|
|
|
spi0@0 {
|
|
pins = "PC0", "PC2", "PC4";
|
|
function = "spi0";
|
|
drive-strength = <0x14>;
|
|
phandle = <0x42>;
|
|
};
|
|
|
|
spi0@1 {
|
|
pins = "PC3";
|
|
function = "spi0";
|
|
drive-strength = <0x14>;
|
|
bias-pull-up;
|
|
phandle = <0x43>;
|
|
};
|
|
|
|
spi0@2 {
|
|
pins = "PC0", "PC2", "PC3", "PC4";
|
|
function = "gpio_in";
|
|
drive-strength = <0x14>;
|
|
phandle = <0x44>;
|
|
};
|
|
|
|
spi1@0 {
|
|
pins = "PH6", "PH7", "PH8";
|
|
function = "spi1";
|
|
drive-strength = <0x14>;
|
|
phandle = <0x45>;
|
|
};
|
|
|
|
spi1@1 {
|
|
pins = "PH9";
|
|
function = "spi1";
|
|
drive-strength = <0x14>;
|
|
bias-pull-up;
|
|
phandle = <0x46>;
|
|
};
|
|
|
|
spi1@2 {
|
|
pins = "PH6", "PH7", "PH8", "PH9";
|
|
function = "gpio_in";
|
|
drive-strength = <0x14>;
|
|
phandle = <0x47>;
|
|
};
|
|
|
|
gmac0@0 {
|
|
pins = "PI0", "PI1", "PI2", "PI3", "PI4", "PI5", "PI7", "PI8", "PI9", "PI10", "PI11", "PI12", "PI13", "PI14", "PI15";
|
|
function = "gmac0";
|
|
drive-strength = <0x1e>;
|
|
bias-pull-up;
|
|
phandle = <0x5e>;
|
|
};
|
|
|
|
gmac0@1 {
|
|
pins = "PI0", "PI1", "PI2", "PI3", "PI4", "PI5", "PI7", "PI8", "PI9", "PI10", "PI11", "PI12", "PI13", "PI14", "PI15";
|
|
function = "gpio_in";
|
|
phandle = <0x5f>;
|
|
};
|
|
|
|
gmac1@0 {
|
|
pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9";
|
|
function = "gmac1";
|
|
drive-strength = <10>;
|
|
bias-pull-up;
|
|
phandle = <0x60>;
|
|
};
|
|
|
|
gmac1@1 {
|
|
pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9";
|
|
function = "gpio_in";
|
|
drive-strength = <10>;
|
|
phandle = <0x61>;
|
|
};
|
|
|
|
pwm5@0 {
|
|
pins = "PA12";
|
|
function = "pwm5";
|
|
drive-strength = <0xa>;
|
|
bias-pull-up;
|
|
phandle = <0x15>;
|
|
};
|
|
|
|
pwm5@1 {
|
|
pins = "PA12";
|
|
function = "gpio_in";
|
|
phandle = <0x16>;
|
|
};
|
|
|
|
spdif@0 {
|
|
pins = "PH4";
|
|
function = "spdif";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x4b>;
|
|
};
|
|
|
|
spdif_sleep@0 {
|
|
pins = "PH4";
|
|
function = "gpio_in";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x4c>;
|
|
};
|
|
|
|
ahub_daudio0@0 {
|
|
pins = "PA6", "PA7", "PA8", "PA9";
|
|
function = "i2s0";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x8b>;
|
|
};
|
|
|
|
ahub_daudio0_sleep@0 {
|
|
pins = "PA6", "PA7", "PA8", "PA9";
|
|
function = "gpio_in";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x8c>;
|
|
};
|
|
|
|
ahub_daudio2@0 {
|
|
pins = "PG11", "PG12";
|
|
function = "i2s2";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x4f>;
|
|
};
|
|
|
|
ahub_daudio2@1 {
|
|
pins = "PG13";
|
|
function = "i2s2_dout0";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x50>;
|
|
};
|
|
|
|
ahub_daudio2@2 {
|
|
pins = "PG14";
|
|
function = "i2s2_din0";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x51>;
|
|
};
|
|
|
|
ahub_daudio2_sleep@0 {
|
|
pins = "PG11", "PG12", "PG13", "PG14";
|
|
function = "gpio_in";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x52>;
|
|
};
|
|
|
|
ahub_daudio3@0 {
|
|
pins = "PH5", "PH6", "PH7";
|
|
function = "i2s3";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x8d>;
|
|
};
|
|
|
|
ahub_daudio3@1 {
|
|
pins = "PH8";
|
|
function = "i2s3_dout0";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x8e>;
|
|
};
|
|
|
|
ahub_daudio3@2 {
|
|
pins = "PH9";
|
|
function = "i2s3_din0";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x8f>;
|
|
};
|
|
|
|
ahub_daudio3_sleep@0 {
|
|
pins = "PH5", "PH6", "PH7", "PH8", "PH9";
|
|
function = "gpio_in";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x90>;
|
|
};
|
|
|
|
standby@0 {
|
|
allwinner,pins = "PH6";
|
|
allwinner,function = "gpio_out";
|
|
allwinner,muxsel = <0x1>;
|
|
allwinner,data = <0x1>;
|
|
allwinner,drive = <0x0>;
|
|
allwinner,pull = <0x0>;
|
|
phandle = <0x91>;
|
|
};
|
|
|
|
standby@1 {
|
|
allwinner,pins = "PH7";
|
|
allwinner,function = "gpio_out";
|
|
allwinner,muxsel = <0x1>;
|
|
allwinner,data = <0x0>;
|
|
allwinner,drive = <0x2>;
|
|
allwinner,pull = <0x2>;
|
|
phandle = <0x92>;
|
|
};
|
|
|
|
standby@2 {
|
|
allwinner,pins = "PG16";
|
|
allwinner,function = "gpio_in";
|
|
allwinner,muxsel = <0x0>;
|
|
allwinner,data = <0x0>;
|
|
allwinner,drive = <0x0>;
|
|
allwinner,pull = <0x0>;
|
|
phandle = <0x93>;
|
|
};
|
|
};
|
|
|
|
pinctrl@7022000 {
|
|
compatible = "allwinner,sun50iw9-r-pinctrl";
|
|
reg = <0x0 0x7022000 0x0 0x400>;
|
|
clocks = <0xd 0x2 0xa 0xb>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
#gpio-cells = <0x3>;
|
|
phandle = <0x94>;
|
|
|
|
s_twi0@0 {
|
|
pins = "PL0", "PL1";
|
|
function = "s_twi0";
|
|
drive-strength = <0x14>;
|
|
bias-pull-up;
|
|
phandle = <0x40>;
|
|
};
|
|
|
|
s_twi0@1 {
|
|
pins = "PL0", "PL1";
|
|
function = "gpio_in";
|
|
phandle = <0x41>;
|
|
};
|
|
};
|
|
|
|
iommu@30f0000 {
|
|
compatible = "allwinner,sunxi-iommu";
|
|
reg = <0x0 0x30f0000 0x0 0x1000>;
|
|
interrupts = <0x0 0x3d 0x4>;
|
|
interrupt-names = "iommu-irq";
|
|
clocks = <0x2 0x30>;
|
|
clock-names = "iommu";
|
|
#iommu-cells = <0x2>;
|
|
phandle = <0x8>;
|
|
};
|
|
|
|
sdmmc@4022000 {
|
|
compatible = "allwinner,sunxi-mmc-v4p6x";
|
|
device_type = "sdc2";
|
|
reg = <0x0 0x4022000 0x0 0x1000>;
|
|
interrupts = <0x0 0x25 0x4>;
|
|
clocks = <0xa 0x2 0x7 0x2 0x3f 0x2 0x42>;
|
|
clock-names = "osc24m", "pll_periph", "mmc", "ahb";
|
|
resets = <0x2 0x10>;
|
|
reset-names = "rst";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x19 0x1a>;
|
|
pinctrl-1 = <0x1b>;
|
|
bus-width = <0x8>;
|
|
req-page-count = <0x2>;
|
|
cap-mmc-highspeed;
|
|
cap-cmd23;
|
|
ctl-spec-caps = <0x308>;
|
|
mmc-cache-ctrl;
|
|
non-removable;
|
|
max-frequency = <0x5f5e100>;
|
|
cap-erase;
|
|
mmc-high-capacity-erase-size;
|
|
no-sdio;
|
|
no-sd;
|
|
sdc_tm4_sm0_freq0 = <0x0>;
|
|
sdc_tm4_sm0_freq1 = <0x0>;
|
|
sdc_tm4_sm1_freq0 = <0x0>;
|
|
sdc_tm4_sm1_freq1 = <0x0>;
|
|
sdc_tm4_sm2_freq0 = <0x0>;
|
|
sdc_tm4_sm2_freq1 = <0x0>;
|
|
sdc_tm4_sm3_freq0 = <0x5000000>;
|
|
sdc_tm4_sm3_freq1 = <0x5>;
|
|
sdc_tm4_sm4_freq0 = <0x50000>;
|
|
sdc_tm4_sm4_freq1 = <0x4>;
|
|
sdc_tm4_sm4_freq0_cmd = <0x0>;
|
|
sdc_tm4_sm4_freq1_cmd = <0x0>;
|
|
status = "disabled";
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
sunxi-dis-signal-vol-sw;
|
|
vmmc-supply = <0x1c>;
|
|
vqmmc-supply = <0x1d>;
|
|
phandle = <0x95>;
|
|
};
|
|
|
|
sdmmc@4020000 {
|
|
compatible = "allwinner,sunxi-mmc-v4p1x";
|
|
device_type = "sdc0";
|
|
reg = <0x0 0x4020000 0x0 0x1000>;
|
|
interrupts = <0x0 0x23 0x4>;
|
|
clocks = <0xa 0x2 0x7 0x2 0x3d 0x2 0x40>;
|
|
clock-names = "osc24m", "pll_periph", "mmc", "ahb";
|
|
resets = <0x2 0xe>;
|
|
reset-names = "rst";
|
|
pinctrl-names = "default", "mmc_1v8", "sleep", "uart_jtag";
|
|
pinctrl-0 = <0x1e>;
|
|
pinctrl-1 = <0x1f>;
|
|
pinctrl-2 = <0x20>;
|
|
pinctrl-3 = <0x21 0x22>;
|
|
max-frequency = <0x8f0d180>;
|
|
bus-width = <0x4>;
|
|
req-page-count = <0x2>;
|
|
ctl-spec-caps = <0x8>;
|
|
cap-sd-highspeed;
|
|
cap-wait-while-busy;
|
|
no-sdio;
|
|
no-mmc;
|
|
status = "okay";
|
|
sd-uhs-sdr50;
|
|
sd-uhs-ddr50;
|
|
sd-uhs-sdr104;
|
|
vmmc-supply = <0x1c>;
|
|
cd-gpios = <0x23 0x5 0x6 0x11>;
|
|
phandle = <0x96>;
|
|
};
|
|
|
|
sdmmc@4021000 {
|
|
compatible = "allwinner,sunxi-mmc-v4p1x";
|
|
device_type = "sdc1";
|
|
reg = <0x0 0x4021000 0x0 0x1000>;
|
|
interrupts = <0x0 0x24 0x4>;
|
|
clocks = <0xa 0x2 0x7 0x2 0x3e 0x2 0x41>;
|
|
clock-names = "osc24m", "pll_periph", "mmc", "ahb";
|
|
resets = <0x2 0xf>;
|
|
reset-names = "rst";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x24>;
|
|
pinctrl-1 = <0x25>;
|
|
max-frequency = <0x8f0d180>;
|
|
bus-width = <0x4>;
|
|
ctl-spec-caps = <0x8>;
|
|
cap-sd-highspeed;
|
|
no-mmc;
|
|
keep-power-in-suspend;
|
|
sunxi-dly-52M-ddr4 = <0x1 0x0 0x0 0x0 0x2>;
|
|
sunxi-dly-104M = <0x1 0x0 0x0 0x0 0x1>;
|
|
sunxi-dly-208M = <0x1 0x0 0x0 0x0 0x1>;
|
|
status = "okay";
|
|
no-sd;
|
|
sd-uhs-sdr12;
|
|
sd-uhs-sdr25;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-ddr50;
|
|
sd-uhs-sdr104;
|
|
sunxi-dis-signal-vol-sw;
|
|
cap-sdio-irq;
|
|
ignore-pm-notify;
|
|
vqmmc-supply = <0x1d>;
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
nand0@4011000 {
|
|
compatible = "allwinner,sun50iw9-nand";
|
|
device_type = "nand0";
|
|
reg = <0x0 0x4011000 0x0 0x1000>;
|
|
interrupts = <0x0 0x22 0x4>;
|
|
clocks = <0x2 0x7 0x2 0x3a 0x2 0x3b 0x2 0x3c 0x2 0x36>;
|
|
clock-names = "pll_periph", "mclk", "ecc", "bus", "mbus";
|
|
resets = <0x2 0xd>;
|
|
reset-names = "rst";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x26 0x27>;
|
|
pinctrl-1 = <0x28>;
|
|
nand0_cache_level = <0x55aaaa55>;
|
|
nand0_flush_cache_num = <0x55aaaa55>;
|
|
nand0_capacity_level = <0x55aaaa55>;
|
|
nand0_id_number_ctl = <0x55aaaa55>;
|
|
nand0_print_level = <0x55aaaa55>;
|
|
nand0_p0 = <0x55aaaa55>;
|
|
nand0_p1 = <0x55aaaa55>;
|
|
nand0_p2 = <0x55aaaa55>;
|
|
nand0_p3 = <0x55aaaa55>;
|
|
chip_code = "sun50iw9";
|
|
status = "disabled";
|
|
nand0_regulator1-supply = <0x1c>;
|
|
nand0_regulator2-supply = <0x1d>;
|
|
phandle = <0x98>;
|
|
};
|
|
|
|
mbus-controller@47fa000 {
|
|
compatible = "allwinner,sun50i-mbus";
|
|
reg = <0x0 0x47fa000 0x0 0x1000>;
|
|
#mbus-cells = <0x1>;
|
|
phandle = <0x99>;
|
|
};
|
|
|
|
uart@5000000 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
reg = <0x0 0x5000000 0x0 0x400>;
|
|
interrupts = <0x0 0x0 0x4>;
|
|
clocks = <0x2 0x43>;
|
|
resets = <0x2 0x11>;
|
|
uart0_port = <0x0>;
|
|
uart0_type = <0x2>;
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x29>;
|
|
pinctrl-1 = <0x2a>;
|
|
phandle = <0x9a>;
|
|
};
|
|
|
|
uart@5000400 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
reg = <0x0 0x5000400 0x0 0x400>;
|
|
interrupts = <0x0 0x1 0x4>;
|
|
clocks = <0x2 0x44>;
|
|
resets = <0x2 0x12>;
|
|
uart1_port = <0x1>;
|
|
uart1_type = <0x4>;
|
|
sunxi,uart-fifosize = <0x100>;
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x2b>;
|
|
pinctrl-1 = <0x2c>;
|
|
device_type = "uart1";
|
|
phandle = <0x9b>;
|
|
};
|
|
|
|
uart@5000800 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
reg = <0x0 0x5000800 0x0 0x400>;
|
|
interrupts = <0x0 0x2 0x4>;
|
|
clocks = <0x2 0x45>;
|
|
resets = <0x2 0x13>;
|
|
uart2_port = <0x2>;
|
|
uart2_type = <0x4>;
|
|
sunxi,uart-fifosize = <0x100>;
|
|
status = "disabled";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x2d>;
|
|
pinctrl-1 = <0x2e>;
|
|
phandle = <0x9c>;
|
|
};
|
|
|
|
uart@5000c00 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
reg = <0x0 0x5000c00 0x0 0x400>;
|
|
interrupts = <0x0 0x3 0x4>;
|
|
clocks = <0x2 0x46>;
|
|
resets = <0x2 0x14>;
|
|
uart3_port = <0x3>;
|
|
uart3_type = <0x4>;
|
|
sunxi,uart-fifosize = <0x100>;
|
|
status = "disabled";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x2f>;
|
|
pinctrl-1 = <0x30>;
|
|
phandle = <0x9d>;
|
|
};
|
|
|
|
uart@5001000 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
reg = <0x0 0x5001000 0x0 0x400>;
|
|
interrupts = <0x0 0x4 0x4>;
|
|
clocks = <0x2 0x47>;
|
|
resets = <0x2 0x15>;
|
|
uart4_port = <0x4>;
|
|
uart4_type = <0x4>;
|
|
sunxi,uart-fifosize = <0x100>;
|
|
status = "disabled";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x31>;
|
|
pinctrl-1 = <0x32>;
|
|
phandle = <0x9e>;
|
|
};
|
|
|
|
uart@5001400 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
reg = <0x0 0x5001400 0x0 0x400>;
|
|
interrupts = <0x0 0x5 0x4>;
|
|
clocks = <0x2 0x48>;
|
|
resets = <0x2 0x16>;
|
|
uart5_port = <0x5>;
|
|
uart5_type = <0x2>;
|
|
sunxi,uart-fifosize = <0x100>;
|
|
status = "disabled";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x33>;
|
|
pinctrl-1 = <0x34>;
|
|
phandle = <0x9f>;
|
|
};
|
|
|
|
twi@5002000 {
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi0";
|
|
reg = <0x0 0x5002000 0x0 0x400>;
|
|
interrupts = <0x0 0x6 0x4>;
|
|
clocks = <0x2 0x49>;
|
|
clock-names = "bus";
|
|
resets = <0x2 0x17>;
|
|
dmas = <0x35 0x2b 0x35 0x2b>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0x36>;
|
|
pinctrl-1 = <0x37>;
|
|
pinctrl-names = "default", "sleep";
|
|
twi_drv_used = <0x1>;
|
|
phandle = <0xa0>;
|
|
|
|
eeprom@50 {
|
|
compatible = "atmel,24c16";
|
|
reg = <0x50>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
twi@5002400 {
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi1";
|
|
reg = <0x0 0x5002400 0x0 0x400>;
|
|
interrupts = <0x0 0x7 0x4>;
|
|
clocks = <0x2 0x4a>;
|
|
clock-names = "bus";
|
|
resets = <0x2 0x18>;
|
|
dmas = <0x35 0x2c 0x35 0x2c>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0x38>;
|
|
pinctrl-1 = <0x39>;
|
|
pinctrl-names = "default", "sleep";
|
|
twi_drv_used = <0x1>;
|
|
phandle = <0xa1>;
|
|
};
|
|
|
|
twi@5002800 {
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi2";
|
|
reg = <0x0 0x5002800 0x0 0x400>;
|
|
interrupts = <0x0 0x8 0x4>;
|
|
clocks = <0x2 0x4b>;
|
|
clock-names = "bus";
|
|
resets = <0x2 0x19>;
|
|
dmas = <0x35 0x2d 0x35 0x2d>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0x3a>;
|
|
pinctrl-1 = <0x3b>;
|
|
pinctrl-names = "default", "sleep";
|
|
twi_drv_used = <0x1>;
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
twi@5002c00 {
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi3";
|
|
reg = <0x0 0x5002c00 0x0 0x400>;
|
|
interrupts = <0x0 0x9 0x4>;
|
|
clocks = <0x2 0x4c>;
|
|
clock-names = "bus";
|
|
resets = <0x2 0x1a>;
|
|
dmas = <0x35 0x2e 0x35 0x2e>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0x3c>;
|
|
pinctrl-1 = <0x3d>;
|
|
pinctrl-names = "default", "sleep";
|
|
twi_drv_used = <0x1>;
|
|
phandle = <0xa3>;
|
|
};
|
|
|
|
twi@5003000 {
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi4";
|
|
reg = <0x0 0x5003000 0x0 0x400>;
|
|
interrupts = <0x0 0xa 0x4>;
|
|
clocks = <0x2 0x4d>;
|
|
clock-names = "bus";
|
|
resets = <0x2 0x1b>;
|
|
dmas = <0x35 0x2f 0x35 0x2f>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0x3e>;
|
|
pinctrl-1 = <0x3f>;
|
|
pinctrl-names = "default", "sleep";
|
|
twi_drv_used = <0x1>;
|
|
phandle = <0xa4>;
|
|
};
|
|
|
|
twi@7081400 {
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi5";
|
|
reg = <0x0 0x7081400 0x0 0x400>;
|
|
interrupts = <0x0 0x69 0x4>;
|
|
clocks = <0xd 0x5>;
|
|
clock-names = "bus";
|
|
resets = <0xd 0x1>;
|
|
dmas = <0x35 0x30 0x35 0x30>;
|
|
dma-names = "tx", "rx";
|
|
status = "okay";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0x40>;
|
|
pinctrl-1 = <0x41>;
|
|
pinctrl-names = "default", "sleep";
|
|
no_suspend = <0x1>;
|
|
twi_drv_used = <0x0>;
|
|
phandle = <0xa5>;
|
|
|
|
pmu {
|
|
compatible = "x-powers,axp1530";
|
|
reg = <0x36>;
|
|
wakeup-source;
|
|
pmu_hot_shutdown = <0x1>;
|
|
phandle = <0xa6>;
|
|
|
|
standby_param {
|
|
vdd-cpua = <0x2>;
|
|
vdd-sys = <0x1>;
|
|
vcc-io = <0x10>;
|
|
vcc-dram = <0x4>;
|
|
phandle = <0xa7>;
|
|
};
|
|
|
|
regulators {
|
|
|
|
dcdc1 {
|
|
regulator-name = "axp1530-dcdc1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x33e140>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-always-on;
|
|
phandle = <0x63>;
|
|
};
|
|
|
|
dcdc2 {
|
|
regulator-name = "axp1530-dcdc2";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x177fa0>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-ramp-delay = <0xc8>;
|
|
regulator-always-on;
|
|
phandle = <0x5>;
|
|
};
|
|
|
|
dcdc3 {
|
|
regulator-name = "axp1530-dcdc3";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x1c1380>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-always-on;
|
|
phandle = <0xa8>;
|
|
};
|
|
|
|
ldo1 {
|
|
regulator-name = "axp1530-aldo1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-always-on;
|
|
phandle = <0x1d>;
|
|
};
|
|
|
|
ldo2 {
|
|
regulator-name = "axp1530-dldo1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-always-on;
|
|
phandle = <0x1c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
spi@5010000 {
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sun50i-spi";
|
|
device_type = "spi0";
|
|
reg = <0x0 0x5010000 0x0 0x1000>;
|
|
interrupts = <0x0 0xc 0x4>;
|
|
clocks = <0x2 0x4 0x2 0x4f 0x2 0x51>;
|
|
clock-names = "pll", "mod", "bus";
|
|
resets = <0x2 0x1d>;
|
|
clock-frequency = <0x5f5e100>;
|
|
spi0_cs_number = <0x1>;
|
|
spi0_cs_bitmap = <0x1>;
|
|
dmas = <0x35 0x16 0x35 0x16>;
|
|
dma-names = "tx", "rx";
|
|
status = "okay";
|
|
spi_slave_mode = <0x0>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x42 0x43>;
|
|
pinctrl-1 = <0x44>;
|
|
spi1_cs_number = <0x1>;
|
|
spi1_cs_bitmap = <0x1>;
|
|
/*spi_dbi_enable = <0x0>;*/
|
|
phandle = <0xa9>;
|
|
|
|
spi_board0 {
|
|
device_type = "spi_board0";
|
|
compatible = "rohm,dh2228fv";
|
|
spi-max-frequency = <0x10000000>;
|
|
reg = <0x0>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
spi@5011000 {
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
compatible = "allwinner,sun50i-spi";
|
|
device_type = "spi1";
|
|
reg = <0x0 0x5011000 0x0 0x1000>;
|
|
interrupts = <0x0 0xd 0x4>;
|
|
clocks = <0x2 0x4 0x2 0x50 0x2 0x52>;
|
|
clock-names = "pll", "mod", "bus";
|
|
resets = <0x2 0x1e>;
|
|
clock-frequency = <0x5f5e100>;
|
|
spi1_cs_number = <0x2>;
|
|
spi1_cs_bitmap = <0x2>;
|
|
dmas = <0x35 0x17 0x35 0x17>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
spi_slave_mode = <0x0>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x45 0x46>;
|
|
pinctrl-1 = <0x47>;
|
|
/*spi_dbi_enable = <0x0>;*/
|
|
phandle = <0xaa>;
|
|
|
|
spi_board1@1 {
|
|
device_type = "spi_board1";
|
|
compatible = "rohm,dh2228fv";
|
|
spi-max-frequency = <0x989680>;
|
|
reg = <0x1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
thermal-sensor@5070400 {
|
|
compatible = "allwinner,sun50iw9p1-ths";
|
|
reg = <0x0 0x5070400 0x0 0x400>;
|
|
clocks = <0x2 0x59>;
|
|
clock-names = "bus";
|
|
resets = <0x2 0x23>;
|
|
nvmem-cells = <0x48>;
|
|
nvmem-cell-names = "calibration";
|
|
#thermal-sensor-cells = <0x1>;
|
|
phandle = <0x74>;
|
|
};
|
|
|
|
gpadc@5070000 {
|
|
compatible = "allwinner,sunxi-gpadc";
|
|
reg = <0x0 0x5070000 0x0 0x3ff>;
|
|
interrupts = <0x0 0x12 0x4>;
|
|
clocks = <0x2 0x58>;
|
|
clock-names = "bus";
|
|
resets = <0x2 0x22>;
|
|
status = "disabled";
|
|
phandle = <0xab>;
|
|
};
|
|
|
|
keyboard@5070800 {
|
|
compatible = "allwinner,keyboard_1350mv";
|
|
reg = <0x0 0x5070800 0x0 0x400>;
|
|
interrupts = <0x0 0x14 0x1>;
|
|
clocks = <0x2 0x74>;
|
|
resets = <0x2 0x35>;
|
|
status = "disabled";
|
|
phandle = <0xac>;
|
|
};
|
|
|
|
codec@5096000 {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-snd-codec";
|
|
reg = <0x0 0x5096000 0x0 0x31c>;
|
|
resets = <0x2 0x26>;
|
|
clocks = <0x2 0x13 0x2 0x5e 0x2 0x60>;
|
|
clock-names = "clk_pll_audio_4x", "clk_audio", "clk_bus_audio";
|
|
status = "okay";
|
|
lineout_vol = <0x1f>;
|
|
pa_pin_max = <0x1>;
|
|
pa_pin_level_0 = <0x1>;
|
|
pa_pin_msleep_0 = <0x0>;
|
|
tx_hub_en;
|
|
phandle = <0x4a>;
|
|
};
|
|
|
|
codec_plat {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-snd-plat-aaudio";
|
|
playback_cma = <0x80>;
|
|
capture_cma = <0x80>;
|
|
tx_fifo_size = <0x80>;
|
|
rx_fifo_size = <0x80>;
|
|
dac_txdata = <0x5096020>;
|
|
adc_txdata = <0x5096040>;
|
|
dmas = <0x35 0x6 0x35 0x6>;
|
|
dma-names = "tx", "rx";
|
|
status = "okay";
|
|
phandle = <0x49>;
|
|
};
|
|
|
|
codec_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "audiocodec";
|
|
soundcard-mach,playback-only;
|
|
soundcard-mach,pin-switches = "LINEOUT";
|
|
soundcard-mach,routing = "LINEOUT", "LINEOUTL", "LINEOUT", "LINEOUTR";
|
|
status = "okay";
|
|
phandle = <0xad>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x49>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
sound-dai = <0x4a>;
|
|
soundcard-mach,pll-fs = <0x4>;
|
|
};
|
|
};
|
|
|
|
spdif_plat@5093000 {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-snd-plat-spdif";
|
|
reg = <0x0 0x5093000 0x0 0x40>;
|
|
resets = <0x2 0x24>;
|
|
clocks = <0x2 0x13 0x2 0x5a 0x2 0x5b>;
|
|
clock-names = "clk_pll_audio_4x", "clk_spdif", "clk_bus_spdif";
|
|
pll-fs = <0x4>;
|
|
dmas = <0x35 0x2 0x35 0x2>;
|
|
dma-names = "tx", "rx";
|
|
playback_cma = <0x80>;
|
|
capture_cma = <0x80>;
|
|
tx_fifo_size = <0x80>;
|
|
rx_fifo_size = <0x40>;
|
|
status = "disabled";
|
|
pinctrl_used;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x4b>;
|
|
pinctrl-1 = <0x4c>;
|
|
tx_hub_en;
|
|
phandle = <0x4d>;
|
|
};
|
|
|
|
spdif_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "sndspdif";
|
|
status = "disabled";
|
|
phandle = <0xae>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x4d>;
|
|
soundcard-mach,pll-fs = <0x4>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
};
|
|
};
|
|
|
|
ahub_dam_plat@5097000 {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-snd-plat-ahub_dam";
|
|
reg = <0x0 0x5097000 0x0 0xaec>;
|
|
resets = <0x2 0x27>;
|
|
clocks = <0x2 0x11 0x2 0x13 0x2 0x61 0x2 0x62>;
|
|
clock-names = "clk_pll_audio", "clk_pll_audio_4x", "clk_audio_hub", "clk_bus_audio_hub";
|
|
status = "okay";
|
|
phandle = <0x4e>;
|
|
};
|
|
|
|
ahub_dam_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "ahubdam";
|
|
status = "disabled";
|
|
phandle = <0xaf>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x4e>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
};
|
|
};
|
|
|
|
ahub0_plat {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-snd-plat-ahub";
|
|
apb_num = <0x0>;
|
|
dmas = <0x35 0x3 0x35 0x3>;
|
|
dma-names = "tx", "rx";
|
|
playback_cma = <0x80>;
|
|
capture_cma = <0x80>;
|
|
tx_fifo_size = <0x80>;
|
|
rx_fifo_size = <0x80>;
|
|
status = "disabled";
|
|
tdm_num = <0x0>;
|
|
tx_pin = <0x0>;
|
|
rx_pin = <0x0>;
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
ahub1_plat {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-snd-plat-ahub";
|
|
apb_num = <0x1>;
|
|
dmas = <0x35 0x4 0x35 0x4>;
|
|
dma-names = "tx", "rx";
|
|
playback_cma = <0x80>;
|
|
capture_cma = <0x80>;
|
|
tx_fifo_size = <0x80>;
|
|
rx_fifo_size = <0x80>;
|
|
status = "okay";
|
|
tdm_num = <0x1>;
|
|
tx_pin = <0x0>;
|
|
rx_pin = <0x0>;
|
|
dai_type = "hdmi";
|
|
phandle = <0x56>;
|
|
};
|
|
|
|
ahub2_plat {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-snd-plat-ahub";
|
|
apb_num = <0x2>;
|
|
dmas = <0x35 0x5 0x35 0x5>;
|
|
dma-names = "tx", "rx";
|
|
playback_cma = <0x80>;
|
|
capture_cma = <0x80>;
|
|
tx_fifo_size = <0x80>;
|
|
rx_fifo_size = <0x80>;
|
|
status = "disabled";
|
|
tdm_num = <0x2>;
|
|
tx_pin = <0x0>;
|
|
rx_pin = <0x0>;
|
|
pinctrl_used;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x4f 0x50 0x51>;
|
|
pinctrl-1 = <0x52>;
|
|
phandle = <0x58>;
|
|
};
|
|
|
|
ahub3_plat {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-snd-plat-ahub";
|
|
apb_num = <0x2>;
|
|
dmas = <0x35 0x5 0x35 0x5>;
|
|
dma-names = "tx", "rx";
|
|
playback_cma = <0x80>;
|
|
capture_cma = <0x80>;
|
|
tx_fifo_size = <0x80>;
|
|
rx_fifo_size = <0x80>;
|
|
status = "disabled";
|
|
tdm_num = <0x3>;
|
|
tx_pin = <0x0>;
|
|
rx_pin = <0x0>;
|
|
phandle = <0x5a>;
|
|
};
|
|
|
|
ahub0_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "ahubi2s0";
|
|
status = "disabled";
|
|
soundcard-mach,format = "i2s";
|
|
soundcard-mach,frame-master = <0x53>;
|
|
soundcard-mach,bitclock-master = <0x53>;
|
|
soundcard-mach,slot-num = <0x2>;
|
|
soundcard-mach,slot-width = <0x20>;
|
|
phandle = <0xb0>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x54>;
|
|
soundcard-mach,pll-fs = <0x4>;
|
|
soundcard-mach,mclk-fs = <0x100>;
|
|
phandle = <0x53>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
phandle = <0xb1>;
|
|
};
|
|
};
|
|
|
|
ahub1_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "ahubhdmi";
|
|
status = "okay";
|
|
soundcard-mach,format = "i2s";
|
|
soundcard-mach,frame-master = <0x55>;
|
|
soundcard-mach,bitclock-master = <0x55>;
|
|
soundcard-mach,slot-num = <0x2>;
|
|
soundcard-mach,slot-width = <0x20>;
|
|
phandle = <0xb2>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x56>;
|
|
soundcard-mach,pll-fs = <0x4>;
|
|
soundcard-mach,mclk-fs = <0x0>;
|
|
phandle = <0x55>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
phandle = <0xb3>;
|
|
};
|
|
};
|
|
|
|
ahub2_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "ahubi2s2";
|
|
status = "okay";
|
|
soundcard-mach,format = "i2s";
|
|
soundcard-mach,frame-master = <0x57>;
|
|
soundcard-mach,bitclock-master = <0x57>;
|
|
soundcard-mach,slot-num = <0x2>;
|
|
soundcard-mach,slot-width = <0x20>;
|
|
phandle = <0xb4>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x58>;
|
|
soundcard-mach,pll-fs = <0x4>;
|
|
soundcard-mach,mclk-fs = <0x100>;
|
|
phandle = <0x57>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
phandle = <0xb5>;
|
|
};
|
|
};
|
|
|
|
ahub3_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "ahubi2s3";
|
|
status = "disabled";
|
|
soundcard-mach,format = "i2s";
|
|
soundcard-mach,frame-master = <0x59>;
|
|
soundcard-mach,bitclock-master = <0x59>;
|
|
soundcard-mach,slot-num = <0x2>;
|
|
soundcard-mach,slot-width = <0x20>;
|
|
phandle = <0xb6>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x5a>;
|
|
soundcard-mach,pll-fs = <0x4>;
|
|
soundcard-mach,mclk-fs = <0x100>;
|
|
phandle = <0x59>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
phandle = <0xb7>;
|
|
};
|
|
};
|
|
|
|
spdif@5094000 {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-spdif";
|
|
reg = <0x0 0x5094000 0x0 0x40>;
|
|
clocks = <0x2 0x11 0x2 0x5a 0x2 0x5b>;
|
|
clock-names = "pll_audio", "spdif", "spdif_bus";
|
|
resets = <0x2 0x24>;
|
|
clk_parent = <0x1>;
|
|
playback_cma = <0x80>;
|
|
capture_cma = <0x80>;
|
|
device_type = "spdif";
|
|
dmas = <0x35 0x2 0x35 0x2>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
phandle = <0x5b>;
|
|
};
|
|
|
|
soundspdif {
|
|
compatible = "sunxi,simple-audio-card";
|
|
simple-audio-card,name = "sndspdif";
|
|
status = "disabled";
|
|
phandle = <0xb8>;
|
|
|
|
simple-audio-card,cpu {
|
|
sound-dai = <0x5b>;
|
|
};
|
|
|
|
simple-audio-card,codec {
|
|
};
|
|
};
|
|
|
|
dmic@5095000 {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "allwinner,sunxi-dmic";
|
|
reg = <0x0 0x5095000 0x0 0x50>;
|
|
clocks = <0x2 0x11 0x2 0x5c 0x2 0x5d>;
|
|
clock-names = "pll_audio", "dmic", "dmic_bus";
|
|
resets = <0x2 0x25>;
|
|
clk_parent = <0x1>;
|
|
capture_cma = <0x100>;
|
|
data_vol = <0xb0>;
|
|
dmic_rxsync_en = <0x0>;
|
|
rx_chmap = <0x76543210>;
|
|
device_type = "dmic";
|
|
dmas = <0x35 0x7>;
|
|
dma-names = "rx";
|
|
status = "disabled";
|
|
phandle = <0x5c>;
|
|
};
|
|
|
|
dmic_codec {
|
|
#sound-dai-cells = <0x0>;
|
|
compatible = "dmic-codec";
|
|
num-channels = <0x8>;
|
|
status = "disabled";
|
|
phandle = <0x5d>;
|
|
};
|
|
|
|
sounddmic {
|
|
compatible = "sunxi,simple-audio-card";
|
|
simple-audio-card,name = "snddmic";
|
|
status = "disabled";
|
|
phandle = <0xb9>;
|
|
|
|
simple-audio-card,cpu {
|
|
sound-dai = <0x5c>;
|
|
};
|
|
|
|
simple-audio-card,codec {
|
|
sound-dai = <0x5d>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
lan_led {
|
|
label = "lan_led";
|
|
gpios = <0x23 0x2 0xb 0x1>; /* PC11 */
|
|
default-state = "off";
|
|
};
|
|
|
|
wan_led {
|
|
label = "wan_led";
|
|
gpios = <0x23 0x2 0xc 0x1>; /* PC12 */
|
|
default-state = "off";
|
|
};
|
|
|
|
status {
|
|
label = "status_led";
|
|
gpios = <0x23 0x2 0xd 0x1>; /* PC13 */
|
|
default-state = "on";
|
|
};
|
|
};
|
|
|
|
gpio_para {
|
|
device_type = "gpio_para";
|
|
compatible = "allwinner,sunxi-init-gpio";
|
|
status = "okay";
|
|
gpio_num = <0x0>;
|
|
/*gpio_pin_1 = <0x23 0x2 0xc 0x1>;
|
|
gpio_pin_2 = <0x23 0x2 0xd 0x0>;*/
|
|
phandle = <0xba>;
|
|
};
|
|
|
|
eth@5020000 {
|
|
compatible = "allwinner,sunxi-gmac";
|
|
reg = <0x0 0x5020000 0x0 0x10000 0x0 0x3000030 0x0 0x4>;
|
|
interrupts = <0x0 0xe 0x4>;
|
|
interrupt-names = "gmacirq";
|
|
clocks = <0x2 0x54 0x2 0x53>;
|
|
clock-names = "gmac", "ephy";
|
|
resets = <0x2 0x1f>;
|
|
device_type = "gmac0";
|
|
phy-mode = "rgmii";
|
|
phy-rst;
|
|
gmac-power0;
|
|
gmac-power1;
|
|
gmac-power2;
|
|
status = "disabled";
|
|
use_ephy25m = <0x0>;
|
|
pinctrl-0 = <0x5e>;
|
|
pinctrl-1 = <0x5f>;
|
|
pinctrl-names = "default", "sleep";
|
|
tx-delay = <0x7>;
|
|
rx-delay = <0x0>;
|
|
phandle = <0xbb>;
|
|
};
|
|
|
|
eth@5030000 {
|
|
compatible = "allwinner,sunxi-gmac";
|
|
reg = <0x0 0x5030000 0x0 0x10000 0x0 0x3000034 0x0 0x4>;
|
|
interrupts = <0x0 0xf 0x4>;
|
|
interrupt-names = "gmacirq";
|
|
clocks = <0x2 0x55>;
|
|
clock-names = "gmac";
|
|
resets = <0x2 0x20>;
|
|
device_type = "gmac1";
|
|
phy-mode = "rmii";
|
|
phy-rst;
|
|
gmac-power0;
|
|
gmac-power1;
|
|
gmac-power2;
|
|
status = "okay";
|
|
pinctrl-0 = <0x60>;
|
|
pinctrl-1 = <0x61>;
|
|
pinctrl-names = "default", "sleep";
|
|
tx-delay = <0x7>;
|
|
rx-delay = <0x1f>;
|
|
phandle = <0xbc>;
|
|
};
|
|
|
|
usbc0@0 {
|
|
device_type = "usbc0";
|
|
compatible = "allwinner,sunxi-otg-manager";
|
|
usb_port_type = <0x0>;
|
|
usb_detect_type = <0x1>;
|
|
usb_detect_mode = <0x0>;
|
|
usb_id_gpio;
|
|
usb_det_vbus_gpio;
|
|
usb_drv_vbus_gpio;
|
|
usb_host_init_state = <0x0>;
|
|
usb_regulator_io = "nocare";
|
|
usb_wakeup_suspend = <0x0>;
|
|
usb_luns = <0x3>;
|
|
usb_serial_unique = <0x0>;
|
|
usb_serial_number = "20080411";
|
|
rndis_wceis = <0x1>;
|
|
wakeup-source;
|
|
status = "okay";
|
|
phandle = <0xbd>;
|
|
};
|
|
|
|
udc-controller@5100000 {
|
|
compatible = "allwinner,sunxi-udc";
|
|
reg = <0x0 0x5100000 0x0 0x1000 0x0 0x0 0x0 0x100>;
|
|
interrupts = <0x0 0x19 0x4>;
|
|
interrupt-parent = <0x7>;
|
|
clocks = <0x2 0x73 0x2 0x64>;
|
|
clock-names = "bus_otg", "phy";
|
|
resets = <0x2 0x34 0x2 0x28>;
|
|
reset-names = "otg", "phy";
|
|
phandle = <0xbe>;
|
|
};
|
|
|
|
ehci0-controller@5101000 {
|
|
compatible = "allwinner,sunxi-ehci0";
|
|
reg = <0x0 0x5101000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
|
|
interrupts = <0x0 0x1a 0x4>;
|
|
clocks = <0x2 0x6f 0x2 0x64>;
|
|
clock-names = "bus_hci", "phy";
|
|
resets = <0x2 0x30 0x2 0x28>;
|
|
reset-names = "hci", "phy";
|
|
hci_ctrl_no = <0x0>;
|
|
status = "okay";
|
|
phandle = <0xbf>;
|
|
};
|
|
|
|
ohci0-controller@5101400 {
|
|
compatible = "allwinner,sunxi-ohci0";
|
|
reg = <0x0 0x5101400 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
|
|
interrupts = <0x0 0x1b 0x4>;
|
|
clocks = <0x2 0x6b 0x2 0x63 0x2 0x64>;
|
|
clock-names = "bus_hci", "ohci", "phy";
|
|
resets = <0x2 0x2c 0x2 0x28>;
|
|
reset-names = "hci", "phy";
|
|
hci_ctrl_no = <0x0>;
|
|
status = "okay";
|
|
phandle = <0xc0>;
|
|
};
|
|
|
|
usbc1@0 {
|
|
device_type = "usbc1";
|
|
usb_drv_vbus_gpio;
|
|
usb_host_init_state = <0x1>;
|
|
usb_regulatior_io = "nocare";
|
|
usb_wakeup_suspend = <0x0>;
|
|
wakeup-source;
|
|
usb_regulator_io = "nocare";
|
|
status = "okay";
|
|
phandle = <0xc1>;
|
|
};
|
|
|
|
ehci1-controller@5200000 {
|
|
compatible = "allwinner,sunxi-ehci1";
|
|
reg = <0x0 0x5200000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
|
|
interrupts = <0x0 0x1c 0x4>;
|
|
clocks = <0x2 0x70 0x2 0x66>;
|
|
clock-names = "bus_hci", "phy";
|
|
resets = <0x2 0x31 0x2 0x29>;
|
|
reset-names = "hci", "phy";
|
|
hci_ctrl_no = <0x1>;
|
|
drvvbus-supply = <0x62>;
|
|
status = "okay";
|
|
phandle = <0xc2>;
|
|
};
|
|
|
|
ohci1-controller@5200400 {
|
|
compatible = "allwinner,sunxi-ohci1";
|
|
reg = <0x0 0x5200400 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
|
|
interrupts = <0x0 0x1d 0x4>;
|
|
clocks = <0x2 0x6c 0x2 0x65 0x2 0x66>;
|
|
clock-names = "bus_hci", "ohci", "phy";
|
|
resets = <0x2 0x2d 0x2 0x29>;
|
|
reset-names = "hci", "phy";
|
|
hci_ctrl_no = <0x1>;
|
|
drvvbus-supply = <0x62>;
|
|
status = "okay";
|
|
phandle = <0xc3>;
|
|
};
|
|
|
|
usbc2@0 {
|
|
device_type = "usbc2";
|
|
usb_drv_vbus_gpio;
|
|
usb_host_init_state = <0x1>;
|
|
usb_regulatior_io = "nocare";
|
|
usb_wakeup_suspend = <0x0>;
|
|
wakeup-source;
|
|
usb_regulator_io = "nocare";
|
|
status = "okay";
|
|
phandle = <0xc4>;
|
|
};
|
|
|
|
ehci2-controller@5310000 {
|
|
compatible = "allwinner,sunxi-ehci2";
|
|
reg = <0x0 0x5310000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
|
|
interrupts = <0x0 0x1e 0x4>;
|
|
clocks = <0x2 0x71 0x2 0x68>;
|
|
clock-names = "bus_hci", "phy";
|
|
resets = <0x2 0x32 0x2 0x2a>;
|
|
reset-names = "hci", "phy";
|
|
hci_ctrl_no = <0x2>;
|
|
drvvbus-supply = <0x62>;
|
|
status = "okay";
|
|
phandle = <0xc5>;
|
|
};
|
|
|
|
ohci2-controller@5310400 {
|
|
compatible = "allwinner,sunxi-ohci2";
|
|
reg = <0x0 0x5310400 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
|
|
interrupts = <0x0 0x1f 0x4>;
|
|
clocks = <0x2 0x6d 0x2 0x67 0x2 0x68>;
|
|
clock-names = "bus_hci", "ohci", "phy";
|
|
resets = <0x2 0x2e 0x2 0x2a>;
|
|
reset-names = "hci", "phy";
|
|
hci_ctrl_no = <0x2>;
|
|
drvvbus-supply = <0x62>;
|
|
status = "okay";
|
|
phandle = <0xc6>;
|
|
};
|
|
|
|
usbc3@0 {
|
|
device_type = "usbc3";
|
|
usb_drv_vbus_gpio;
|
|
usb_host_init_state = <0x1>;
|
|
usb_regulatior_io = "nocare";
|
|
usb_wakeup_suspend = <0x0>;
|
|
wakeup-source;
|
|
usb_regulator_io = "nocare";
|
|
status = "okay";
|
|
phandle = <0xc7>;
|
|
};
|
|
|
|
ehci3-controller@5311000 {
|
|
compatible = "allwinner,sunxi-ehci3";
|
|
reg = <0x0 0x5311000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
|
|
interrupts = <0x0 0x20 0x4>;
|
|
clocks = <0x2 0x72 0x2 0x6a>;
|
|
clock-names = "bus_hci", "phy";
|
|
resets = <0x2 0x33 0x2 0x2b>;
|
|
reset-names = "hci", "phy";
|
|
hci_ctrl_no = <0x3>;
|
|
drvvbus-supply = <0x62>;
|
|
status = "okay";
|
|
phandle = <0xc8>;
|
|
};
|
|
|
|
ohci3-controller@5311400 {
|
|
compatible = "allwinner,sunxi-ohci3";
|
|
reg = <0x0 0x5311400 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
|
|
interrupts = <0x0 0x21 0x4>;
|
|
clocks = <0x2 0x6e 0x2 0x69 0x2 0x6a>;
|
|
clock-names = "bus_hci", "ohci", "phy";
|
|
resets = <0x2 0x2f 0x2 0x2b>;
|
|
reset-names = "hci", "phy";
|
|
hci_ctrl_no = <0x3>;
|
|
drvvbus-supply = <0x62>;
|
|
status = "okay";
|
|
phandle = <0xc9>;
|
|
};
|
|
|
|
hdmi@6000000 {
|
|
compatible = "allwinner,sunxi-hdmi";
|
|
reg = <0x0 0x6000000 0x0 0x100000>;
|
|
interrupts = <0x0 0x3f 0x4>;
|
|
clocks = <0x2 0x79 0x2 0x75 0x2 0x76 0x2 0x78 0x2 0x8b 0x2 0x8a 0x2 0x7f>;
|
|
clock-names = "clk_bus_hdmi", "clk_hdmi", "clk_ddc", "clk_cec", "clk_bus_hdcp", "clk_hdcp", "clk_tcon_tv";
|
|
resets = <0x2 0x37 0x2 0x36 0x2 0x41>;
|
|
reset-names = "rst_bus_sub", "rst_bus_main", "rst_bus_hdcp";
|
|
assigned-clocks = <0x2 0x75 0x2 0x8a>;
|
|
assigned-clock-parents = <0x2 0xd 0x2 0x6>;
|
|
assigned-clock-rates = <0x0 0x0>;
|
|
status = "okay";
|
|
hdmi_used = <0x1>;
|
|
aldo1-supply = <0x1d>;
|
|
dcdc1-supply = <0x63>;
|
|
hdmi_power_cnt = <0x2>;
|
|
hdmi_power0 = "aldo1";
|
|
hdmi_power1 = "dcdc1";
|
|
hdmi_hdcp_enable = <0x1>;
|
|
hdmi_hdcp22_enable = <0x1>;
|
|
hdmi_cts_compatibility = <0x0>;
|
|
hdmi_cec_support = <0x1>;
|
|
hdmi_cec_super_standby = <0x0>;
|
|
ddc_en_io_ctrl = <0x0>;
|
|
power_io_ctrl = <0x0>;
|
|
phandle = <0xca>;
|
|
};
|
|
|
|
interrupt-controller@7010320 {
|
|
compatible = "allwinner,sun8i-nmi";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
reg = <0x0 0x7010320 0x0 0xc>;
|
|
interrupts = <0x0 0x67 0x4>;
|
|
pad-control-v1 = <0x7000208>;
|
|
phandle = <0xcb>;
|
|
};
|
|
|
|
boot_init_gpio {
|
|
device_type = "boot_init_gpio";
|
|
status = "okay";
|
|
//gpio0 = <0x53 0x2 0xb 0x1 0xffffffff 0xffffffff 0x0>;
|
|
gpio0 = <0x53 0x2 0xc 0x1 0xffffffff 0xffffffff 0x0>;
|
|
gpio1 = <0x53 0x2 0xd 0x1 0xffffffff 0xffffffff 0x1>;
|
|
};
|
|
|
|
s_cir@7040000 {
|
|
compatible = "allwinner,s_cir";
|
|
reg = <0x0 0x7040000 0x0 0x400>;
|
|
interrupts = <0x0 0x6a 0x4>;
|
|
clocks = <0xd 0x8 0xa 0xd 0x7>;
|
|
clock-names = "bus", "pclk", "mclk";
|
|
resets = <0xd 0x3>;
|
|
status = "okay";
|
|
s_cir0_used = <0x1>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x64>;
|
|
pinctrl-1 = <0x65>;
|
|
ir_power_key_code0 = <0x40>;
|
|
ir_addr_code0 = <0xfe01>;
|
|
ir_power_key_code1 = <0x1a>;
|
|
ir_addr_code1 = <0xfb04>;
|
|
ir_power_key_code2 = <0xf2>;
|
|
ir_addr_code2 = <0x2992>;
|
|
ir_power_key_code3 = <0x57>;
|
|
ir_addr_code3 = <0x9f00>;
|
|
ir_power_key_code4 = <0xdc>;
|
|
ir_addr_code4 = <0x4cb3>;
|
|
ir_power_key_code5 = <0x18>;
|
|
ir_addr_code5 = <0xff00>;
|
|
ir_power_key_code6 = <0xdc>;
|
|
ir_addr_code6 = <0xdd22>;
|
|
ir_power_key_code7 = <0xd>;
|
|
ir_addr_code7 = <0xbc00>;
|
|
ir_power_key_code8 = <0x4d>;
|
|
ir_addr_code8 = <0x4040>;
|
|
wakeup-source;
|
|
phandle = <0xcc>;
|
|
};
|
|
|
|
rfkill {
|
|
compatible = "allwinner,sunxi-rfkill";
|
|
status = "okay";
|
|
chip_en;
|
|
power_en;
|
|
pinctrl-0;
|
|
pinctrl-names;
|
|
clocks;
|
|
phandle = <0xcd>;
|
|
|
|
wlan {
|
|
compatible = "allwinner,sunxi-wlan";
|
|
wlan_busnum = <0x1>;
|
|
wlan_power;
|
|
wlan_regon = <0x23 0x6 0x12 0x0>;
|
|
wlan_hostwake = <0x23 0x6 0xf 0x0>;
|
|
wakeup-source;
|
|
phandle = <0xce>;
|
|
};
|
|
|
|
bt {
|
|
compatible = "allwinner,sunxi-bt";
|
|
bt_power;
|
|
bt_rst_n = <0x23 0x6 0x13 0x1>;
|
|
phandle = <0xcf>;
|
|
};
|
|
};
|
|
|
|
addr_mgt {
|
|
compatible = "allwinner,sunxi-addr_mgt";
|
|
status = "okay";
|
|
type_addr_wifi = <0x0>;
|
|
type_addr_bt = <0x0>;
|
|
type_addr_eth = <0x0>;
|
|
phandle = <0xd0>;
|
|
};
|
|
|
|
btlpm {
|
|
compatible = "allwinner,sunxi-btlpm";
|
|
status = "okay";
|
|
uart_index = <0x1>;
|
|
bt_wake = <0x23 0x6 0x11 0x0>;
|
|
bt_hostwake = <0x23 0x6 0x10 0x0>;
|
|
wakeup-source;
|
|
phandle = <0xd1>;
|
|
};
|
|
|
|
card0_boot_para@2 {
|
|
reg = <0x0 0x2 0x0 0x0>;
|
|
device_type = "card0_boot_para";
|
|
card_ctrl = <0x0>;
|
|
card_high_speed = <0x1>;
|
|
card_line = <0x4>;
|
|
pinctrl-0 = <0x1e>;
|
|
};
|
|
|
|
card2_boot_para@3 {
|
|
reg = <0x0 0x3 0x0 0x0>;
|
|
device_type = "card2_boot_para";
|
|
card_ctrl = <0x2>;
|
|
card_high_speed = <0x1>;
|
|
card_line = <0x8>;
|
|
pinctrl-0 = <0x19 0x1a>;
|
|
sdc_ex_dly_used = <0x2>;
|
|
sdc_io_1v8 = <0x1>;
|
|
sdc_type = "tm4";
|
|
};
|
|
|
|
pll_video2 {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "new";
|
|
assigned-clocks = <0x66>;
|
|
clock-output-names = "pll_video2";
|
|
phandle = <0x66>;
|
|
};
|
|
|
|
pll_de {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,pll-clock";
|
|
assigned-clocks = <0x67>;
|
|
assigned-clock-rates = <0x297c1e00>;
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_de";
|
|
phandle = <0x67>;
|
|
};
|
|
|
|
de {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <0x67>;
|
|
assigned-clock-rates = <0x297c1e00>;
|
|
assigned-clocks = <0x68>;
|
|
clock-output-names = "de";
|
|
phandle = <0x68>;
|
|
};
|
|
|
|
display_top {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "display_top";
|
|
phandle = <0x70>;
|
|
};
|
|
|
|
tcon_lcd {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "tcon_lcd";
|
|
phandle = <0x71>;
|
|
};
|
|
|
|
tcon_lcd1 {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "tcon_lcd1";
|
|
phandle = <0x72>;
|
|
};
|
|
|
|
tcon_tv {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <0x66>;
|
|
assigned-clocks = <0x69>;
|
|
clock-output-names = "tcon_tv";
|
|
phandle = <0x69>;
|
|
};
|
|
|
|
tcon_tv1 {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "tcon_tv1";
|
|
phandle = <0x73>;
|
|
};
|
|
|
|
lvds {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "lvds";
|
|
assigned-clocks = <0x6a>;
|
|
phandle = <0x6a>;
|
|
};
|
|
|
|
hdmi {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <0x66>;
|
|
assigned-clocks = <0x6b>;
|
|
clock-output-names = "hdmi";
|
|
phandle = <0x6b>;
|
|
};
|
|
|
|
hdmi_slow {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clocks = <0x6c>;
|
|
clock-output-names = "hdmi_slow";
|
|
phandle = <0x6c>;
|
|
};
|
|
|
|
hdmi_cec {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clocks = <0x6d>;
|
|
clock-output-names = "hdmi_cec";
|
|
phandle = <0x6d>;
|
|
};
|
|
|
|
hdmi_hdcp {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <0x6e>;
|
|
assigned-clocks = <0x6f>;
|
|
clock-output-names = "hdmi_hdcp";
|
|
phandle = <0x6f>;
|
|
};
|
|
|
|
pll_periph1 {
|
|
#clock-cells = <0x0>;
|
|
compatible = "allwinner,pll-clock";
|
|
assigned-clocks = <0x6e>;
|
|
assigned-clock-rates = <0x23c34600>;
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_periph1";
|
|
phandle = <0x6e>;
|
|
};
|
|
|
|
auto_print@54321 {
|
|
reg = <0x0 0x54321 0x0 0x0>;
|
|
device_type = "auto_print";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
uboot_disp@1000000 {
|
|
compatible = "allwinner,sunxi-disp";
|
|
reg = <0x0 0x1000000 0x0 0x1400000 0x0 0x6510000 0x0 0x200 0x0 0x6511000 0x0 0x1000 0x0 0x6512000 0x0 0x1000 0x0 0x6515000 0x0 0x1000 0x0 0x6516000 0x0 0x1000>;
|
|
interrupts = <0x0 0x58 0x4 0x0 0x40 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4>;
|
|
clocks = <0x68 0x70 0x71 0x72 0x69 0x73 0x6a>;
|
|
boot_disp = <0x0>;
|
|
fb_base = <0x0>;
|
|
phandle = <0xd2>;
|
|
};
|
|
|
|
uboot_hdmi@6000000 {
|
|
compatible = "allwinner,sunxi-hdmi";
|
|
reg = <0x0 0x6000000 0x0 0x100000>;
|
|
interrupts = <0x0 0x3f 0x4>;
|
|
clocks = <0x6b 0x6c 0x6f 0x6d>;
|
|
phandle = <0xd3>;
|
|
};
|
|
|
|
thermal-zones {
|
|
|
|
cpu_thermal_zone {
|
|
polling-delay-passive = <0x1f4>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x74 0x2>;
|
|
sustainable-power = <0x39f>;
|
|
|
|
trips {
|
|
phandle = <0xd4>;
|
|
|
|
trip-point@0 {
|
|
temperature = <0x11170>;
|
|
type = "passive";
|
|
hysteresis = <0x0>;
|
|
phandle = <0xd5>;
|
|
};
|
|
|
|
trip-point@1 {
|
|
temperature = <0x15f90>;
|
|
type = "passive";
|
|
hysteresis = <0x0>;
|
|
phandle = <0x75>;
|
|
};
|
|
|
|
cpu_crit@0 {
|
|
temperature = <0x1c138>;
|
|
type = "critical";
|
|
hysteresis = <0x0>;
|
|
phandle = <0xd6>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x75>;
|
|
cooling-device = <0x76 0xffffffff 0xffffffff>;
|
|
contribution = <0x400>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x75>;
|
|
cooling-device = <0x77 0xffffffff 0xffffffff>;
|
|
contribution = <0x400>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ddr_thermal_zone {
|
|
polling-delay-passive = <0x0>;
|
|
polling-delay = <0x0>;
|
|
thermal-sensors = <0x74 0x3>;
|
|
};
|
|
|
|
gpu_thermal_zone {
|
|
polling-delay-passive = <0x1f4>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x74 0x0>;
|
|
sustainable-power = <0x44c>;
|
|
};
|
|
|
|
ve_thermal_zone {
|
|
polling-delay-passive = <0x0>;
|
|
polling-delay = <0x0>;
|
|
thermal-sensors = <0x74 0x1>;
|
|
};
|
|
};
|
|
|
|
usb0-drvvvbus {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "usb0-drvvbus";
|
|
regulator-min-microvolt = <0x4c4b40>;
|
|
regulator-max-microvolt = <0x4c4b40>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
gpio = <0x23 0x2 0x10 0x0>;
|
|
enable-active-high;
|
|
phandle = <0x62>;
|
|
};
|
|
|
|
box_start_os0 {
|
|
compatible = "allwinner,box_start_os";
|
|
start_type = <0x1>;
|
|
irkey_used = <0x0>;
|
|
pmukey_used = <0x0>;
|
|
pmukey_num = <0x0>;
|
|
led_power = <0x0>;
|
|
led_state = <0x0>;
|
|
};
|
|
|
|
__symbols__ {
|
|
cpu0 = "/cpus/cpu@0";
|
|
CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
|
|
cpu_opp_table = "/cpu-opp-table";
|
|
dump_reg = "/dump-reg@20000";
|
|
iosc = "/internal-osc-clk";
|
|
dcxo24M = "/dcxo24M-clk";
|
|
osc32k = "/osc32k-clk";
|
|
gic = "/interrupt-controller@3021000";
|
|
wakeupgen = "/interrupt-controller@0";
|
|
reg_pio1_8 = "/pio-18";
|
|
reg_pio3_3 = "/pio-33";
|
|
dram = "/dram";
|
|
soc = "/soc@3000000";
|
|
disp = "/soc@3000000/disp@1000000";
|
|
ve = "/soc@3000000/ve@1c0e000";
|
|
ve1 = "/soc@3000000/ve1@1c0e000";
|
|
g2d = "/soc@3000000/g2d@1480000";
|
|
di = "/soc@3000000/deinterlace@1420000";
|
|
gpu = "/soc@3000000/gpu@1800000";
|
|
ipa_dvfs = "/soc@3000000/gpu@1800000/ipa_dvfs";
|
|
lcd0 = "/soc@3000000/lcd0@1c0c000";
|
|
tv0 = "/soc@3000000/tv0@6520000";
|
|
ccu = "/soc@3000000/ccu@3001000";
|
|
rtc_ccu = "/soc@3000000/rtc_ccu@7000000";
|
|
rtc = "/soc@3000000/rtc@7000000";
|
|
r_ccu = "/soc@3000000/r_ccu@7010000";
|
|
dma = "/soc@3000000/dma-controller@3002000";
|
|
sram_ctrl = "/soc@3000000/sram_ctrl@3000000";
|
|
speedbin_efuse = "/soc@3000000/sid@3006000/speed@00";
|
|
ths_calib = "/soc@3000000/sid@3006000/calib@14";
|
|
tvout = "/soc@3000000/sid@3006000/tvout@2e";
|
|
i_cpu_efuse = "/soc@3000000/sid@3006000/i-cpu@28";
|
|
cryptoengine = "/soc@3000000/ce@1904000";
|
|
soc_timer0 = "/soc@3000000/timer@3009000";
|
|
wdt = "/soc@3000000/watchdog@30090a0";
|
|
pwm = "/soc@3000000/pwm@300a000";
|
|
pwm0 = "/soc@3000000/pwm0@300a010";
|
|
pwm1 = "/soc@3000000/pwm1@300a011";
|
|
pwm2 = "/soc@3000000/pwm2@300a012";
|
|
pwm3 = "/soc@3000000/pwm3@300a013";
|
|
pwm4 = "/soc@3000000/pwm4@300a014";
|
|
pwm5 = "/soc@3000000/pwm5@300a015";
|
|
ac200 = "/soc@3000000/ac200";
|
|
pio = "/soc@3000000/pinctrl@300b000";
|
|
uart0_ph_pins = "/soc@3000000/pinctrl@300b000/uart0-ph-pins";
|
|
uart0_ph_sleep = "/soc@3000000/pinctrl@300b000/uart0-ph-sleep";
|
|
sdc0_pins_a = "/soc@3000000/pinctrl@300b000/sdc0@0";
|
|
sdc0_pins_b = "/soc@3000000/pinctrl@300b000/sdc0@1";
|
|
sdc0_pins_c = "/soc@3000000/pinctrl@300b000/sdc0@2";
|
|
sdc0_pins_d = "/soc@3000000/pinctrl@300b000/sdc0@3";
|
|
sdc0_pins_e = "/soc@3000000/pinctrl@300b000/sdc0@4";
|
|
sdc1_pins_a = "/soc@3000000/pinctrl@300b000/sdc1@0";
|
|
sdc1_pins_b = "/soc@3000000/pinctrl@300b000/sdc1@1";
|
|
sdc2_pins_a = "/soc@3000000/pinctrl@300b000/sdc2@0";
|
|
sdc2_pins_b = "/soc@3000000/pinctrl@300b000/sdc2@1";
|
|
sdc2_pins_c = "/soc@3000000/pinctrl@300b000/sdc2@2";
|
|
nand0_pins_a = "/soc@3000000/pinctrl@300b000/nand0@0";
|
|
nand0_pins_b = "/soc@3000000/pinctrl@300b000/nand0@1";
|
|
nand0_pins_c = "/soc@3000000/pinctrl@300b000/nand0@2";
|
|
uart1_ph_pins = "/soc@3000000/pinctrl@300b000/uart1-ph-pins";
|
|
uart1_ph_sleep = "/soc@3000000/pinctrl@300b000/uart1-ph-sleep";
|
|
uart2_ph_pins = "/soc@3000000/pinctrl@300b000/uart2-ph-pins";
|
|
uart2_ph_sleep = "/soc@3000000/pinctrl@300b000/uart2-ph-sleep";
|
|
uart3_ph_pins = "/soc@3000000/pinctrl@300b000/uart3-ph-pins";
|
|
uart3_ph_sleep = "/soc@3000000/pinctrl@300b000/uart3-ph-sleep";
|
|
uart4_ph_pins = "/soc@3000000/pinctrl@300b000/uart4-ph-pins";
|
|
uart4_ph_sleep = "/soc@3000000/pinctrl@300b000/uart4-ph-sleep";
|
|
uart5_ph_pins = "/soc@3000000/pinctrl@300b000/uart5-ph-pins";
|
|
uart5_ph_sleep = "/soc@3000000/pinctrl@300b000/uart5-ph-sleep";
|
|
s_cir0_pins_a = "/soc@3000000/pinctrl@300b000/s_cir0@0";
|
|
s_cir0_pins_b = "/soc@3000000/pinctrl@300b000/s_cir0@1";
|
|
twi0_pins_a = "/soc@3000000/pinctrl@300b000/twi0@0";
|
|
twi0_pins_b = "/soc@3000000/pinctrl@300b000/twi0@1";
|
|
twi1_pins_a = "/soc@3000000/pinctrl@300b000/twi1@0";
|
|
twi1_pins_b = "/soc@3000000/pinctrl@300b000/twi1@1";
|
|
twi2_pins_a = "/soc@3000000/pinctrl@300b000/twi2@0";
|
|
twi2_pins_b = "/soc@3000000/pinctrl@300b000/twi2@1";
|
|
twi3_pins_a = "/soc@3000000/pinctrl@300b000/twi3@0";
|
|
twi3_pins_b = "/soc@3000000/pinctrl@300b000/twi3@1";
|
|
twi4_pins_a = "/soc@3000000/pinctrl@300b000/twi4@0";
|
|
twi4_pins_b = "/soc@3000000/pinctrl@300b000/twi4@1";
|
|
spi0_pins_a = "/soc@3000000/pinctrl@300b000/spi0@0";
|
|
spi0_pins_b = "/soc@3000000/pinctrl@300b000/spi0@1";
|
|
spi0_pins_c = "/soc@3000000/pinctrl@300b000/spi0@2";
|
|
spi1_pins_a = "/soc@3000000/pinctrl@300b000/spi1@0";
|
|
spi1_pins_b = "/soc@3000000/pinctrl@300b000/spi1@1";
|
|
spi1_pins_c = "/soc@3000000/pinctrl@300b000/spi1@2";
|
|
gmac0_pins_a = "/soc@3000000/pinctrl@300b000/gmac0@0";
|
|
gmac0_pins_b = "/soc@3000000/pinctrl@300b000/gmac0@1";
|
|
gmac1_pins_a = "/soc@3000000/pinctrl@300b000/gmac1@0";
|
|
gmac1_pins_b = "/soc@3000000/pinctrl@300b000/gmac1@1";
|
|
pwm5_pin_a = "/soc@3000000/pinctrl@300b000/pwm5@0";
|
|
pwm5_pin_b = "/soc@3000000/pinctrl@300b000/pwm5@1";
|
|
spdif_pins_a = "/soc@3000000/pinctrl@300b000/spdif@0";
|
|
spdif_pins_b = "/soc@3000000/pinctrl@300b000/spdif_sleep@0";
|
|
ahub_daudio0_pins_a = "/soc@3000000/pinctrl@300b000/ahub_daudio0@0";
|
|
ahub_daudio0_pins_b = "/soc@3000000/pinctrl@300b000/ahub_daudio0_sleep@0";
|
|
ahub_daudio2_pins_a = "/soc@3000000/pinctrl@300b000/ahub_daudio2@0";
|
|
ahub_daudio2_pins_b = "/soc@3000000/pinctrl@300b000/ahub_daudio2@1";
|
|
ahub_daudio2_pins_c = "/soc@3000000/pinctrl@300b000/ahub_daudio2@2";
|
|
ahub_daudio2_pins_d = "/soc@3000000/pinctrl@300b000/ahub_daudio2_sleep@0";
|
|
ahub_daudio3_pins_a = "/soc@3000000/pinctrl@300b000/ahub_daudio3@0";
|
|
ahub_daudio3_pins_b = "/soc@3000000/pinctrl@300b000/ahub_daudio3@1";
|
|
ahub_daudio3_pins_c = "/soc@3000000/pinctrl@300b000/ahub_daudio3@2";
|
|
ahub_daudio3_pins_d = "/soc@3000000/pinctrl@300b000/ahub_daudio3_sleep@0";
|
|
standby_red = "/soc@3000000/pinctrl@300b000/standby@0";
|
|
standby_blue = "/soc@3000000/pinctrl@300b000/standby@1";
|
|
standby_bt = "/soc@3000000/pinctrl@300b000/standby@2";
|
|
r_pio = "/soc@3000000/pinctrl@7022000";
|
|
s_twi0_pins_a = "/soc@3000000/pinctrl@7022000/s_twi0@0";
|
|
s_twi0_pins_b = "/soc@3000000/pinctrl@7022000/s_twi0@1";
|
|
mmu_aw = "/soc@3000000/iommu@30f0000";
|
|
sdc2 = "/soc@3000000/sdmmc@4022000";
|
|
sdc0 = "/soc@3000000/sdmmc@4020000";
|
|
sdc1 = "/soc@3000000/sdmmc@4021000";
|
|
nand0 = "/soc@3000000/nand0@4011000";
|
|
mbus0 = "/soc@3000000/mbus-controller@47fa000";
|
|
uart0 = "/soc@3000000/uart@5000000";
|
|
uart1 = "/soc@3000000/uart@5000400";
|
|
uart2 = "/soc@3000000/uart@5000800";
|
|
uart3 = "/soc@3000000/uart@5000c00";
|
|
uart4 = "/soc@3000000/uart@5001000";
|
|
uart5 = "/soc@3000000/uart@5001400";
|
|
twi0 = "/soc@3000000/twi@5002000";
|
|
twi1 = "/soc@3000000/twi@5002400";
|
|
twi2 = "/soc@3000000/twi@5002800";
|
|
twi3 = "/soc@3000000/twi@5002c00";
|
|
twi4 = "/soc@3000000/twi@5003000";
|
|
twi5 = "/soc@3000000/twi@7081400";
|
|
pmu0 = "/soc@3000000/twi@7081400/pmu";
|
|
standby_param = "/soc@3000000/twi@7081400/pmu/standby_param";
|
|
reg_dcdc1 = "/soc@3000000/twi@7081400/pmu/regulators/dcdc1";
|
|
reg_dcdc2 = "/soc@3000000/twi@7081400/pmu/regulators/dcdc2";
|
|
reg_dcdc3 = "/soc@3000000/twi@7081400/pmu/regulators/dcdc3";
|
|
reg_aldo1 = "/soc@3000000/twi@7081400/pmu/regulators/ldo1";
|
|
reg_dldo1 = "/soc@3000000/twi@7081400/pmu/regulators/ldo2";
|
|
spi0 = "/soc@3000000/spi@5010000";
|
|
spi1 = "/soc@3000000/spi@5011000";
|
|
ths = "/soc@3000000/thermal-sensor@5070400";
|
|
gpadc = "/soc@3000000/gpadc@5070000";
|
|
keyboard = "/soc@3000000/keyboard@5070800";
|
|
codec = "/soc@3000000/codec@5096000";
|
|
codec_plat = "/soc@3000000/codec_plat";
|
|
codec_mach = "/soc@3000000/codec_mach";
|
|
spdif_plat = "/soc@3000000/spdif_plat@5093000";
|
|
spdif_mach = "/soc@3000000/spdif_mach";
|
|
ahub_dam_plat = "/soc@3000000/ahub_dam_plat@5097000";
|
|
ahub_dam_mach = "/soc@3000000/ahub_dam_mach";
|
|
ahub0_plat = "/soc@3000000/ahub0_plat";
|
|
ahub1_plat = "/soc@3000000/ahub1_plat";
|
|
ahub2_plat = "/soc@3000000/ahub2_plat";
|
|
ahub3_plat = "/soc@3000000/ahub3_plat";
|
|
ahub0_mach = "/soc@3000000/ahub0_mach";
|
|
ahub0_cpu = "/soc@3000000/ahub0_mach/soundcard-mach,cpu";
|
|
ahub0_codec = "/soc@3000000/ahub0_mach/soundcard-mach,codec";
|
|
ahub1_mach = "/soc@3000000/ahub1_mach";
|
|
ahub1_cpu = "/soc@3000000/ahub1_mach/soundcard-mach,cpu";
|
|
ahub1_codec = "/soc@3000000/ahub1_mach/soundcard-mach,codec";
|
|
ahub2_mach = "/soc@3000000/ahub2_mach";
|
|
ahub2_cpu = "/soc@3000000/ahub2_mach/soundcard-mach,cpu";
|
|
ahub2_codec = "/soc@3000000/ahub2_mach/soundcard-mach,codec";
|
|
ahub3_mach = "/soc@3000000/ahub3_mach";
|
|
ahub3_cpu = "/soc@3000000/ahub3_mach/soundcard-mach,cpu";
|
|
ahub3_codec = "/soc@3000000/ahub3_mach/soundcard-mach,codec";
|
|
spdif = "/soc@3000000/spdif@5094000";
|
|
soundspdif = "/soc@3000000/soundspdif";
|
|
dmic = "/soc@3000000/dmic@5095000";
|
|
dmic_codec = "/soc@3000000/dmic_codec";
|
|
sounddmic = "/soc@3000000/sounddmic";
|
|
gpio_para = "/soc@3000000/gpio_para";
|
|
gmac0 = "/soc@3000000/eth@5020000";
|
|
gmac1 = "/soc@3000000/eth@5030000";
|
|
usbc0 = "/soc@3000000/usbc0@0";
|
|
udc = "/soc@3000000/udc-controller@5100000";
|
|
ehci0 = "/soc@3000000/ehci0-controller@5101000";
|
|
ohci0 = "/soc@3000000/ohci0-controller@5101400";
|
|
usbc1 = "/soc@3000000/usbc1@0";
|
|
ehci1 = "/soc@3000000/ehci1-controller@5200000";
|
|
ohci1 = "/soc@3000000/ohci1-controller@5200400";
|
|
usbc2 = "/soc@3000000/usbc2@0";
|
|
ehci2 = "/soc@3000000/ehci2-controller@5310000";
|
|
ohci2 = "/soc@3000000/ohci2-controller@5310400";
|
|
usbc3 = "/soc@3000000/usbc3@0";
|
|
ehci3 = "/soc@3000000/ehci3-controller@5311000";
|
|
ohci3 = "/soc@3000000/ohci3-controller@5311400";
|
|
hdmi = "/soc@3000000/hdmi@6000000";
|
|
nmi_intc = "/soc@3000000/interrupt-controller@7010320";
|
|
s_cir0 = "/soc@3000000/s_cir@7040000";
|
|
rfkill = "/soc@3000000/rfkill";
|
|
wlan = "/soc@3000000/rfkill/wlan";
|
|
bt = "/soc@3000000/rfkill/bt";
|
|
addr_mgt = "/soc@3000000/addr_mgt";
|
|
btlpm = "/soc@3000000/btlpm";
|
|
clk_pll_video2 = "/soc@3000000/pll_video2";
|
|
clk_pll_de = "/soc@3000000/pll_de";
|
|
clk_de = "/soc@3000000/de";
|
|
clk_display_top = "/soc@3000000/display_top";
|
|
clk_tcon_lcd = "/soc@3000000/tcon_lcd";
|
|
clk_tcon_lcd1 = "/soc@3000000/tcon_lcd1";
|
|
clk_tcon_tv = "/soc@3000000/tcon_tv";
|
|
clk_tcon_tv1 = "/soc@3000000/tcon_tv1";
|
|
clk_lvds = "/soc@3000000/lvds";
|
|
clk_hdmi = "/soc@3000000/hdmi";
|
|
clk_hdmi_slow = "/soc@3000000/hdmi_slow";
|
|
clk_hdmi_cec = "/soc@3000000/hdmi_cec";
|
|
clk_hdmi_hdcp = "/soc@3000000/hdmi_hdcp";
|
|
clk_pll_periph1 = "/soc@3000000/pll_periph1";
|
|
uboot_disp = "/uboot_disp@1000000";
|
|
uboot_hdmi = "/uboot_hdmi@6000000";
|
|
cpu_trips = "/thermal-zones/cpu_thermal_zone/trips";
|
|
cpu_threshold = "/thermal-zones/cpu_thermal_zone/trips/trip-point@0";
|
|
cpu_target = "/thermal-zones/cpu_thermal_zone/trips/trip-point@1";
|
|
cpu_crit = "/thermal-zones/cpu_thermal_zone/trips/cpu_crit@0";
|
|
usb0_drvvbus = "/usb0-drvvvbus";
|
|
};
|
|
};
|