8146 lines
216 KiB
Plaintext
8146 lines
216 KiB
Plaintext
/dts-v1/;
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/ {
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model = "sun55iw3";
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interrupt-parent = <0x01>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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board = "A527\0A527-PRO2-AXP717C";
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compatible = "allwinner,a523\0arm,sun55iw3p1";
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aliases {
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serial0 = "/soc@3000000/uart@2500000";
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serial1 = "/soc@3000000/uart@2500400";
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serial2 = "/soc@3000000/uart@2500800";
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serial3 = "/soc@3000000/uart@2500c00";
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serial4 = "/soc@3000000/uart@2501000";
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serial5 = "/soc@3000000/uart@2501400";
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serial6 = "/soc@3000000/uart@2501800";
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serial7 = "/soc@3000000/uart@2501c00";
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serial8 = "/soc@3000000/uart@7080000";
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serial9 = "/soc@3000000/uart@7080400";
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ir0 = "/soc@3000000/irrx@2005000";
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ir1 = "/soc@3000000/s_irrx@7040000";
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ir2 = "/soc@3000000/irtx@2003000";
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pcie = "/soc@3000000/pcie@4800000";
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gpadc0 = "/soc@3000000/gpadc0@2009000";
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gpadc1 = "/soc@3000000/gpadc1@2009c00";
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twi0 = "/soc@3000000/twi0@2502000";
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twi1 = "/soc@3000000/twi1@2502400";
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twi2 = "/soc@3000000/twi2@2502800";
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twi3 = "/soc@3000000/twi3@2502c00";
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twi4 = "/soc@3000000/twi4@2503000";
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twi5 = "/soc@3000000/twi5@2503400";
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twi6 = "/soc@3000000/s_twi0@7081400";
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twi7 = "/soc@3000000/s_twi1@7081800";
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twi8 = "/soc@3000000/s_twi2@7081c00";
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spi0 = "/soc@3000000/spi@4025000";
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spi1 = "/soc@3000000/spi@4026000";
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spi2 = "/soc@3000000/spi@4027000";
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spi3 = "/soc@3000000/spi@7092000";
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spif0 = "/soc@3000000/spif@47f0000";
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nand0 = "/soc@3000000/nand0@4011000";
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ve0 = "/soc@3000000/ve@1c0e000";
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ve1 = "/soc@3000000/ve1@1c0e000";
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sunxi-mmc0 = "/soc@3000000/sdmmc@4020000";
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sunxi-mmc2 = "/soc@3000000/sdmmc@4022000";
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gmac0 = "/soc@3000000/gmac0@4500000";
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gmac1 = "/soc@3000000/ethernet@4510000";
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edp0 = "/soc@3000000/edp0@5720000";
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nsi0 = "/soc@3000000/nsi-controller@2020000";
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npu = "/soc@3000000/npu@7122000";
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pmu0 = "/soc@3000000/s_twi0@7081400/pmu@35";
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axp1530 = "/soc@3000000/s_twi0@7081400/axp1530@36";
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lcd0 = "/soc@3000000/lcd0@1c0c000";
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hdmi = "/soc@3000000/hdmi@5520000";
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reg-axp1530 = "/soc@3000000/s_twi0@7081400/axp1530@36/regulators/dcdc1";
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cpu-ext = "/cpus/cpu@400";
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standby-param = "/standby_param";
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arisc-config = "/arisc_config";
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};
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vdd-sys {
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compatible = "regulator-fixed";
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regulator-name = "vdd_sys";
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regulator-min-microvolt = <0xdbba0>;
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regulator-max-microvolt = <0xdbba0>;
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regulator-boot-on;
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regulator-always-on;
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phandle = <0x1d>;
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};
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reserved-memory {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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bl31 {
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reg = <0x00 0x48000000 0x00 0x1000000>;
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};
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};
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firmware {
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android {
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compatible = "android,firmware";
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boot_devices = "soc@3000000/4020000.sdmmc,soc@3000000/4022000.sdmmc,soc@3000000";
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vbmeta {
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compatible = "android,vbmeta";
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parts = "vbmeta,vbmeta_system,vbmeta_vendor,boot,init_boot";
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};
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};
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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cpus {
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x00 0x00>;
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enable-method = "psci";
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cpu-idle-states = <0x02 0x03>;
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capacity-dmips-mhz = <0x39a>;
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clocks = <0x04 0x01>;
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operating-points-v2 = <0x05>;
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#cooling-cells = <0x02>;
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dynamic-power-coefficient = <0x11e>;
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cpu-supply = <0x06>;
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phandle = <0x09>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x00 0x100>;
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enable-method = "psci";
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cpu-idle-states = <0x02 0x03>;
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capacity-dmips-mhz = <0x39a>;
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clocks = <0x04 0x01>;
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operating-points-v2 = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x0a>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x00 0x200>;
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enable-method = "psci";
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cpu-idle-states = <0x02 0x03>;
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capacity-dmips-mhz = <0x39a>;
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clocks = <0x04 0x01>;
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operating-points-v2 = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x0b>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x00 0x300>;
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enable-method = "psci";
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cpu-idle-states = <0x02 0x03>;
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capacity-dmips-mhz = <0x39a>;
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clocks = <0x04 0x01>;
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operating-points-v2 = <0x05>;
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#cooling-cells = <0x02>;
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phandle = <0x0c>;
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};
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cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x00 0x400>;
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enable-method = "psci";
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cpu-idle-states = <0x02 0x03>;
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capacity-dmips-mhz = <0x400>;
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clocks = <0x04 0x03>;
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operating-points-v2 = <0x07>;
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#cooling-cells = <0x02>;
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dynamic-power-coefficient = <0x162>;
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cpu-supply = <0x08>;
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phandle = <0x0d>;
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};
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cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x00 0x500>;
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enable-method = "psci";
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cpu-idle-states = <0x02 0x03>;
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capacity-dmips-mhz = <0x400>;
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clocks = <0x04 0x03>;
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operating-points-v2 = <0x07>;
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#cooling-cells = <0x02>;
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phandle = <0x0e>;
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};
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cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x00 0x600>;
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enable-method = "psci";
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cpu-idle-states = <0x02 0x03>;
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capacity-dmips-mhz = <0x400>;
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clocks = <0x04 0x03>;
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operating-points-v2 = <0x07>;
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#cooling-cells = <0x02>;
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phandle = <0x0f>;
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};
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cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x00 0x700>;
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enable-method = "psci";
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cpu-idle-states = <0x02 0x03>;
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capacity-dmips-mhz = <0x400>;
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clocks = <0x04 0x03>;
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operating-points-v2 = <0x07>;
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#cooling-cells = <0x02>;
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phandle = <0x10>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x09>;
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};
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core1 {
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cpu = <0x0a>;
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};
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core2 {
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cpu = <0x0b>;
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};
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core3 {
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cpu = <0x0c>;
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};
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};
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cluster1 {
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core0 {
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cpu = <0x0d>;
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};
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core1 {
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cpu = <0x0e>;
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};
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core2 {
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cpu = <0x0f>;
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};
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core3 {
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cpu = <0x10>;
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};
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};
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};
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idle-states {
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entry-method = "arm,psci";
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cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x10000>;
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entry-latency-us = <0x2e>;
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exit-latency-us = <0x3b>;
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min-residency-us = <0xdf2>;
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local-timer-stop;
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phandle = <0x02>;
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};
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cluster-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <0x2f>;
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exit-latency-us = <0x4a>;
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min-residency-us = <0x1388>;
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local-timer-stop;
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phandle = <0x03>;
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};
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};
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};
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vf_mapping_table {
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vf-version = "V0.71";
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table = <0x00 0x00 0x01 0x100 0x21 0x102 0x02 0x200 0x12 0x201 0x04 0x300 0x14 0x301 0x24 0x302 0x05 0x400 0x06 0x500 0x26 0x502>;
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phandle = <0x12c>;
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};
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gpu_vf_mapping_table {
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table = <0x01 0x01 0x02 0x02 0x12 0x15 0x04 0x03 0x14 0x1f 0x05 0x04 0x06 0x05>;
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phandle = <0x12d>;
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};
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npu_vf_mapping_table {
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table = <0x01 0x01 0x21 0x0c 0x02 0x02 0x12 0x15 0x04 0x03 0x14 0x1f 0x24 0x20 0x05 0x04 0x06 0x05 0x26 0x34>;
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phandle = <0x12e>;
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};
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cluster0-opp-table {
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compatible = "allwinner,sun50i-operating-points";
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opp-shared;
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phandle = <0x05>;
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opp@408000000 {
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opp-hz = <0x00 0x18519600>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0xdbba0>;
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opp-microvolt-vf0100 = <0xdbba0>;
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opp-microvolt-vf0102 = <0xdbba0>;
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opp-microvolt-vf0200 = <0xdbba0>;
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opp-microvolt-vf0201 = <0xdbba0>;
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opp-microvolt-vf0300 = <0xdbba0>;
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opp-microvolt-vf0301 = <0xdbba0>;
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opp-microvolt-vf0302 = <0xdbba0>;
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opp-microvolt-vf0400 = <0xdbba0>;
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opp-microvolt-vf0500 = <0xdbba0>;
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opp-microvolt-vf0502 = <0xdbba0>;
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};
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opp@672000000 {
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opp-hz = <0x00 0x280de800>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0x00>;
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opp-microvolt-vf0100 = <0xdbba0>;
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opp-microvolt-vf0102 = <0xdbba0>;
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opp-microvolt-vf0200 = <0xdbba0>;
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opp-microvolt-vf0201 = <0xdbba0>;
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opp-microvolt-vf0300 = <0xdbba0>;
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opp-microvolt-vf0301 = <0xdbba0>;
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opp-microvolt-vf0302 = <0xdbba0>;
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opp-microvolt-vf0400 = <0xdbba0>;
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opp-microvolt-vf0500 = <0xdbba0>;
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opp-microvolt-vf0502 = <0xdbba0>;
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};
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opp@720000000 {
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opp-hz = <0x00 0x2aea5400>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0xdbba0>;
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opp-microvolt-vf0100 = <0x00>;
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opp-microvolt-vf0102 = <0x00>;
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opp-microvolt-vf0200 = <0x00>;
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opp-microvolt-vf0201 = <0x00>;
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opp-microvolt-vf0300 = <0x00>;
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opp-microvolt-vf0301 = <0x00>;
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opp-microvolt-vf0302 = <0x00>;
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opp-microvolt-vf0400 = <0x00>;
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opp-microvolt-vf0500 = <0x00>;
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opp-microvolt-vf0502 = <0x00>;
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};
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opp@792000000 {
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opp-hz = <0x00 0x2f34f600>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0x00>;
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opp-microvolt-vf0100 = <0xdbba0>;
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opp-microvolt-vf0102 = <0xdbba0>;
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opp-microvolt-vf0200 = <0xdbba0>;
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opp-microvolt-vf0201 = <0xdbba0>;
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opp-microvolt-vf0300 = <0xdbba0>;
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opp-microvolt-vf0301 = <0xdbba0>;
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opp-microvolt-vf0302 = <0xdbba0>;
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opp-microvolt-vf0400 = <0xdbba0>;
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opp-microvolt-vf0500 = <0xdbba0>;
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opp-microvolt-vf0502 = <0xdbba0>;
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};
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opp@936000000 {
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opp-hz = <0x00 0x37ca3a00>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0xdbba0>;
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opp-microvolt-vf0100 = <0xe09c0>;
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opp-microvolt-vf0102 = <0xe09c0>;
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opp-microvolt-vf0200 = <0xe09c0>;
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opp-microvolt-vf0201 = <0xe09c0>;
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opp-microvolt-vf0300 = <0xdbba0>;
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opp-microvolt-vf0301 = <0xdbba0>;
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opp-microvolt-vf0302 = <0xdbba0>;
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opp-microvolt-vf0400 = <0xdbba0>;
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opp-microvolt-vf0500 = <0xdbba0>;
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opp-microvolt-vf0502 = <0xdbba0>;
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};
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opp@1008000000 {
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opp-hz = <0x00 0x3c14dc00>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0x00>;
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opp-microvolt-vf0100 = <0xea600>;
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opp-microvolt-vf0102 = <0xea600>;
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opp-microvolt-vf0200 = <0xea600>;
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opp-microvolt-vf0201 = <0xea600>;
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opp-microvolt-vf0300 = <0xe09c0>;
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opp-microvolt-vf0301 = <0xe09c0>;
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opp-microvolt-vf0302 = <0xe09c0>;
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opp-microvolt-vf0400 = <0x00>;
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opp-microvolt-vf0500 = <0xe09c0>;
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opp-microvolt-vf0502 = <0xe09c0>;
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};
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opp@1032000000 {
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opp-hz = <0x00 0x3d831200>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0x00>;
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opp-microvolt-vf0100 = <0x00>;
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opp-microvolt-vf0102 = <0x00>;
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opp-microvolt-vf0200 = <0x00>;
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opp-microvolt-vf0201 = <0x00>;
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opp-microvolt-vf0300 = <0x00>;
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opp-microvolt-vf0301 = <0x00>;
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opp-microvolt-vf0302 = <0x00>;
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opp-microvolt-vf0400 = <0xe09c0>;
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opp-microvolt-vf0500 = <0x00>;
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opp-microvolt-vf0502 = <0x00>;
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};
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opp@1104000000 {
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opp-hz = <0x00 0x41cdb400>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0x00>;
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opp-microvolt-vf0100 = <0xf4240>;
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opp-microvolt-vf0102 = <0x00>;
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opp-microvolt-vf0200 = <0xf4240>;
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opp-microvolt-vf0201 = <0xf4240>;
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opp-microvolt-vf0300 = <0xea600>;
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opp-microvolt-vf0301 = <0xea600>;
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opp-microvolt-vf0302 = <0x00>;
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opp-microvolt-vf0400 = <0x00>;
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opp-microvolt-vf0500 = <0xea600>;
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opp-microvolt-vf0502 = <0x00>;
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};
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opp@1128000000 {
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opp-hz = <0x00 0x433bea00>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0xf4240>;
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opp-microvolt-vf0100 = <0x00>;
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opp-microvolt-vf0102 = <0x00>;
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opp-microvolt-vf0200 = <0x00>;
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opp-microvolt-vf0201 = <0x00>;
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opp-microvolt-vf0300 = <0x00>;
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opp-microvolt-vf0301 = <0x00>;
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opp-microvolt-vf0302 = <0x00>;
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opp-microvolt-vf0400 = <0xea600>;
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opp-microvolt-vf0500 = <0x00>;
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opp-microvolt-vf0502 = <0x00>;
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};
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opp@1224000000 {
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opp-hz = <0x00 0x48f4c200>;
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clock-latency-ns = <0x3b9b0>;
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opp-microvolt-vf0000 = <0x100590>;
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opp-microvolt-vf0100 = <0x100590>;
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opp-microvolt-vf0102 = <0x00>;
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opp-microvolt-vf0200 = <0x100590>;
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opp-microvolt-vf0201 = <0x100590>;
|
|
opp-microvolt-vf0300 = <0xf4240>;
|
|
opp-microvolt-vf0301 = <0xf4240>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0xf4240>;
|
|
opp-microvolt-vf0500 = <0xf4240>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1296000000 {
|
|
opp-hz = <0x00 0x4d3f6400>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x10c8e0>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x00>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1320000000 {
|
|
opp-hz = <0x00 0x4ead9a00>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0x111700>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x111700>;
|
|
opp-microvolt-vf0201 = <0x111700>;
|
|
opp-microvolt-vf0300 = <0x100590>;
|
|
opp-microvolt-vf0301 = <0x100590>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x100590>;
|
|
opp-microvolt-vf0500 = <0x100590>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1416000000 {
|
|
opp-hz = <0x00 0x54667200>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x118c30>;
|
|
opp-microvolt-vf0100 = <0x118c30>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x118c30>;
|
|
opp-microvolt-vf0201 = <0x118c30>;
|
|
opp-microvolt-vf0300 = <0x10c8e0>;
|
|
opp-microvolt-vf0301 = <0x10c8e0>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x10c8e0>;
|
|
opp-microvolt-vf0500 = <0x10c8e0>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
};
|
|
|
|
cluster1-opp-table {
|
|
compatible = "allwinner,sun50i-operating-points";
|
|
opp-shared;
|
|
phandle = <0x07>;
|
|
|
|
opp@408000000 {
|
|
opp-hz = <0x00 0x18519600>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0xdbba0>;
|
|
opp-microvolt-vf0100 = <0xdbba0>;
|
|
opp-microvolt-vf0102 = <0xdbba0>;
|
|
opp-microvolt-vf0200 = <0xdbba0>;
|
|
opp-microvolt-vf0201 = <0xdbba0>;
|
|
opp-microvolt-vf0300 = <0xdbba0>;
|
|
opp-microvolt-vf0301 = <0xdbba0>;
|
|
opp-microvolt-vf0302 = <0xdbba0>;
|
|
opp-microvolt-vf0400 = <0xdbba0>;
|
|
opp-microvolt-vf0500 = <0xdbba0>;
|
|
opp-microvolt-vf0502 = <0xdbba0>;
|
|
};
|
|
|
|
opp@672000000 {
|
|
opp-hz = <0x00 0x280de800>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xdbba0>;
|
|
opp-microvolt-vf0102 = <0xdbba0>;
|
|
opp-microvolt-vf0200 = <0xdbba0>;
|
|
opp-microvolt-vf0201 = <0xdbba0>;
|
|
opp-microvolt-vf0300 = <0xdbba0>;
|
|
opp-microvolt-vf0301 = <0xdbba0>;
|
|
opp-microvolt-vf0302 = <0xdbba0>;
|
|
opp-microvolt-vf0400 = <0xdbba0>;
|
|
opp-microvolt-vf0500 = <0xdbba0>;
|
|
opp-microvolt-vf0502 = <0xdbba0>;
|
|
};
|
|
|
|
opp@720000000 {
|
|
opp-hz = <0x00 0x2aea5400>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0xdbba0>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x00>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@840000000 {
|
|
opp-hz = <0x00 0x32116200>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xdbba0>;
|
|
opp-microvolt-vf0102 = <0xdbba0>;
|
|
opp-microvolt-vf0200 = <0xdbba0>;
|
|
opp-microvolt-vf0201 = <0xdbba0>;
|
|
opp-microvolt-vf0300 = <0xdbba0>;
|
|
opp-microvolt-vf0301 = <0xdbba0>;
|
|
opp-microvolt-vf0302 = <0xdbba0>;
|
|
opp-microvolt-vf0400 = <0xdbba0>;
|
|
opp-microvolt-vf0500 = <0xdbba0>;
|
|
opp-microvolt-vf0502 = <0xdbba0>;
|
|
};
|
|
|
|
opp@1008000000 {
|
|
opp-hz = <0x00 0x3c14dc00>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xdbba0>;
|
|
opp-microvolt-vf0102 = <0xdbba0>;
|
|
opp-microvolt-vf0200 = <0xdbba0>;
|
|
opp-microvolt-vf0201 = <0xdbba0>;
|
|
opp-microvolt-vf0300 = <0xdbba0>;
|
|
opp-microvolt-vf0301 = <0xdbba0>;
|
|
opp-microvolt-vf0302 = <0xdbba0>;
|
|
opp-microvolt-vf0400 = <0xdbba0>;
|
|
opp-microvolt-vf0500 = <0xdbba0>;
|
|
opp-microvolt-vf0502 = <0xdbba0>;
|
|
};
|
|
|
|
opp@1200000000 {
|
|
opp-hz = <0x00 0x47868c00>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xe09c0>;
|
|
opp-microvolt-vf0102 = <0xe09c0>;
|
|
opp-microvolt-vf0200 = <0xe09c0>;
|
|
opp-microvolt-vf0201 = <0xe09c0>;
|
|
opp-microvolt-vf0300 = <0xe09c0>;
|
|
opp-microvolt-vf0301 = <0xe09c0>;
|
|
opp-microvolt-vf0302 = <0xe09c0>;
|
|
opp-microvolt-vf0400 = <0xe09c0>;
|
|
opp-microvolt-vf0500 = <0xe09c0>;
|
|
opp-microvolt-vf0502 = <0xe09c0>;
|
|
};
|
|
|
|
opp@1248000000 {
|
|
opp-hz = <0x00 0x4a62f800>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0xdbba0>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x00>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1344000000 {
|
|
opp-hz = <0x00 0x501bd000>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xea600>;
|
|
opp-microvolt-vf0102 = <0xea600>;
|
|
opp-microvolt-vf0200 = <0xea600>;
|
|
opp-microvolt-vf0201 = <0xea600>;
|
|
opp-microvolt-vf0300 = <0xea600>;
|
|
opp-microvolt-vf0301 = <0xea600>;
|
|
opp-microvolt-vf0302 = <0xea600>;
|
|
opp-microvolt-vf0400 = <0xea600>;
|
|
opp-microvolt-vf0500 = <0xea600>;
|
|
opp-microvolt-vf0502 = <0xea600>;
|
|
};
|
|
|
|
opp@1488000000 {
|
|
opp-hz = <0x00 0x58b11400>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0xf4240>;
|
|
opp-microvolt-vf0100 = <0xf4240>;
|
|
opp-microvolt-vf0102 = <0xf4240>;
|
|
opp-microvolt-vf0200 = <0xf4240>;
|
|
opp-microvolt-vf0201 = <0xf4240>;
|
|
opp-microvolt-vf0300 = <0xf4240>;
|
|
opp-microvolt-vf0301 = <0xf4240>;
|
|
opp-microvolt-vf0302 = <0xf4240>;
|
|
opp-microvolt-vf0400 = <0xf4240>;
|
|
opp-microvolt-vf0500 = <0xf4240>;
|
|
opp-microvolt-vf0502 = <0xf4240>;
|
|
};
|
|
|
|
opp@1584000000 {
|
|
opp-hz = <0x00 0x5e69ec00>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x100590>;
|
|
opp-microvolt-vf0100 = <0x100590>;
|
|
opp-microvolt-vf0102 = <0x100590>;
|
|
opp-microvolt-vf0200 = <0x100590>;
|
|
opp-microvolt-vf0201 = <0x100590>;
|
|
opp-microvolt-vf0300 = <0x100590>;
|
|
opp-microvolt-vf0301 = <0x100590>;
|
|
opp-microvolt-vf0302 = <0x100590>;
|
|
opp-microvolt-vf0400 = <0x100590>;
|
|
opp-microvolt-vf0500 = <0x100590>;
|
|
opp-microvolt-vf0502 = <0x100590>;
|
|
};
|
|
|
|
opp@1680000000 {
|
|
opp-hz = <0x00 0x6422c400>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x10c8e0>;
|
|
opp-microvolt-vf0100 = <0x10c8e0>;
|
|
opp-microvolt-vf0102 = <0x10c8e0>;
|
|
opp-microvolt-vf0200 = <0x10c8e0>;
|
|
opp-microvolt-vf0201 = <0x10c8e0>;
|
|
opp-microvolt-vf0300 = <0x10c8e0>;
|
|
opp-microvolt-vf0301 = <0x10c8e0>;
|
|
opp-microvolt-vf0302 = <0x10c8e0>;
|
|
opp-microvolt-vf0400 = <0x10c8e0>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1800000000 {
|
|
opp-hz = <0x00 0x6b49d200>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x118c30>;
|
|
opp-microvolt-vf0100 = <0x118c30>;
|
|
opp-microvolt-vf0102 = <0x118c30>;
|
|
opp-microvolt-vf0200 = <0x118c30>;
|
|
opp-microvolt-vf0201 = <0x118c30>;
|
|
opp-microvolt-vf0300 = <0x118c30>;
|
|
opp-microvolt-vf0301 = <0x118c30>;
|
|
opp-microvolt-vf0302 = <0x118c30>;
|
|
opp-microvolt-vf0400 = <0x118c30>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1992000000 {
|
|
opp-hz = <0x00 0x76bb8200>;
|
|
clock-latency-ns = <0x3b9b0>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x129da0>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
};
|
|
|
|
dsufreq@0 {
|
|
compatible = "allwinner,sun55iw3-dsufreq";
|
|
reg = <0x00 0x8815000 0x00 0x1000>;
|
|
clocks = <0x04 0x02>;
|
|
operating-points-v2 = <0x11>;
|
|
dsu-supply = <0x06>;
|
|
phandle = <0x12f>;
|
|
};
|
|
|
|
dsu-opp-table {
|
|
compatible = "allwinner,dsu-operating-points";
|
|
phandle = <0x11>;
|
|
|
|
opp@288000000 {
|
|
opp-hz = <0x00 0x112a8800>;
|
|
opp-microvolt-vf0000 = <0xdbba0>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x00>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@408000000 {
|
|
opp-hz = <0x00 0x18519600>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xdbba0>;
|
|
opp-microvolt-vf0102 = <0xdbba0>;
|
|
opp-microvolt-vf0200 = <0xdbba0>;
|
|
opp-microvolt-vf0201 = <0xdbba0>;
|
|
opp-microvolt-vf0300 = <0xdbba0>;
|
|
opp-microvolt-vf0301 = <0xdbba0>;
|
|
opp-microvolt-vf0302 = <0xdbba0>;
|
|
opp-microvolt-vf0400 = <0xdbba0>;
|
|
opp-microvolt-vf0500 = <0xdbba0>;
|
|
opp-microvolt-vf0502 = <0xdbba0>;
|
|
};
|
|
|
|
opp@528000000 {
|
|
opp-hz = <0x00 0x1f78a400>;
|
|
opp-microvolt-vf0000 = <0xdbba0>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x00>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@600000000 {
|
|
opp-hz = <0x00 0x23c34600>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xdbba0>;
|
|
opp-microvolt-vf0102 = <0xdbba0>;
|
|
opp-microvolt-vf0200 = <0xdbba0>;
|
|
opp-microvolt-vf0201 = <0xdbba0>;
|
|
opp-microvolt-vf0300 = <0xdbba0>;
|
|
opp-microvolt-vf0301 = <0xdbba0>;
|
|
opp-microvolt-vf0302 = <0xdbba0>;
|
|
opp-microvolt-vf0400 = <0xdbba0>;
|
|
opp-microvolt-vf0500 = <0xdbba0>;
|
|
opp-microvolt-vf0502 = <0xdbba0>;
|
|
};
|
|
|
|
opp@696000000 {
|
|
opp-hz = <0x00 0x297c1e00>;
|
|
opp-microvolt-vf0000 = <0xdbba0>;
|
|
opp-microvolt-vf0100 = <0xdbba0>;
|
|
opp-microvolt-vf0102 = <0xdbba0>;
|
|
opp-microvolt-vf0200 = <0xdbba0>;
|
|
opp-microvolt-vf0201 = <0xdbba0>;
|
|
opp-microvolt-vf0300 = <0xdbba0>;
|
|
opp-microvolt-vf0301 = <0xdbba0>;
|
|
opp-microvolt-vf0302 = <0xdbba0>;
|
|
opp-microvolt-vf0400 = <0xdbba0>;
|
|
opp-microvolt-vf0500 = <0xdbba0>;
|
|
opp-microvolt-vf0502 = <0xdbba0>;
|
|
};
|
|
|
|
opp@792000000 {
|
|
opp-hz = <0x00 0x2f34f600>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xe09c0>;
|
|
opp-microvolt-vf0102 = <0xe09c0>;
|
|
opp-microvolt-vf0200 = <0xe09c0>;
|
|
opp-microvolt-vf0201 = <0xe09c0>;
|
|
opp-microvolt-vf0300 = <0xdbba0>;
|
|
opp-microvolt-vf0301 = <0xdbba0>;
|
|
opp-microvolt-vf0302 = <0xdbba0>;
|
|
opp-microvolt-vf0400 = <0xdbba0>;
|
|
opp-microvolt-vf0500 = <0xdbba0>;
|
|
opp-microvolt-vf0502 = <0xdbba0>;
|
|
};
|
|
|
|
opp@864000000 {
|
|
opp-hz = <0x00 0x337f9800>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xea600>;
|
|
opp-microvolt-vf0102 = <0xea600>;
|
|
opp-microvolt-vf0200 = <0xea600>;
|
|
opp-microvolt-vf0201 = <0xea600>;
|
|
opp-microvolt-vf0300 = <0xe09c0>;
|
|
opp-microvolt-vf0301 = <0xe09c0>;
|
|
opp-microvolt-vf0302 = <0xe09c0>;
|
|
opp-microvolt-vf0400 = <0xe09c0>;
|
|
opp-microvolt-vf0500 = <0xe09c0>;
|
|
opp-microvolt-vf0502 = <0xe09c0>;
|
|
};
|
|
|
|
opp@936000000 {
|
|
opp-hz = <0x00 0x37ca3a00>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0xf4240>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0xf4240>;
|
|
opp-microvolt-vf0201 = <0xf4240>;
|
|
opp-microvolt-vf0300 = <0xea600>;
|
|
opp-microvolt-vf0301 = <0xea600>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0xea600>;
|
|
opp-microvolt-vf0500 = <0xea600>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@984000000 {
|
|
opp-hz = <0x00 0x3aa6a600>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0x100590>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x100590>;
|
|
opp-microvolt-vf0201 = <0x100590>;
|
|
opp-microvolt-vf0300 = <0xf4240>;
|
|
opp-microvolt-vf0301 = <0xf4240>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0xf4240>;
|
|
opp-microvolt-vf0500 = <0xf4240>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1008000000 {
|
|
opp-hz = <0x00 0x3c14dc00>;
|
|
opp-microvolt-vf0000 = <0xf4240>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x00>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1056000000 {
|
|
opp-hz = <0x00 0x3ef14800>;
|
|
opp-microvolt-vf0000 = <0x00>;
|
|
opp-microvolt-vf0100 = <0x111700>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x111700>;
|
|
opp-microvolt-vf0201 = <0x111700>;
|
|
opp-microvolt-vf0300 = <0x100590>;
|
|
opp-microvolt-vf0301 = <0x100590>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x100590>;
|
|
opp-microvolt-vf0500 = <0x100590>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1104000000 {
|
|
opp-hz = <0x00 0x41cdb400>;
|
|
opp-microvolt-vf0000 = <0x100590>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x00>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1128000000 {
|
|
opp-hz = <0x00 0x433bea00>;
|
|
opp-microvolt-vf0000 = <0x10c8e0>;
|
|
opp-microvolt-vf0100 = <0x00>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x00>;
|
|
opp-microvolt-vf0201 = <0x00>;
|
|
opp-microvolt-vf0300 = <0x00>;
|
|
opp-microvolt-vf0301 = <0x00>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x00>;
|
|
opp-microvolt-vf0500 = <0x00>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
|
|
opp@1152000000 {
|
|
opp-hz = <0x00 0x44aa2000>;
|
|
opp-microvolt-vf0000 = <0x118c30>;
|
|
opp-microvolt-vf0100 = <0x118c30>;
|
|
opp-microvolt-vf0102 = <0x00>;
|
|
opp-microvolt-vf0200 = <0x118c30>;
|
|
opp-microvolt-vf0201 = <0x118c30>;
|
|
opp-microvolt-vf0300 = <0x10c8e0>;
|
|
opp-microvolt-vf0301 = <0x10c8e0>;
|
|
opp-microvolt-vf0302 = <0x00>;
|
|
opp-microvolt-vf0400 = <0x10c8e0>;
|
|
opp-microvolt-vf0500 = <0x10c8e0>;
|
|
opp-microvolt-vf0502 = <0x00>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
|
|
cpul_thermal_zone {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x12 0x01>;
|
|
sustainable-power = <0x4b0>;
|
|
phandle = <0x130>;
|
|
|
|
trips {
|
|
phandle = <0x131>;
|
|
|
|
trip-point@0 {
|
|
temperature = <0x11170>;
|
|
type = "passive";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x132>;
|
|
};
|
|
|
|
trip-point@1 {
|
|
temperature = <0x15f90>;
|
|
type = "passive";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x13>;
|
|
};
|
|
|
|
cpu_crit@0 {
|
|
temperature = <0x1adb0>;
|
|
type = "critical";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x133>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x13>;
|
|
cooling-device = <0x09 0xffffffff 0xffffffff>;
|
|
contribution = <0x400>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpub_thermal_zone {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x12 0x00>;
|
|
sustainable-power = <0x640>;
|
|
phandle = <0x134>;
|
|
|
|
trips {
|
|
phandle = <0x135>;
|
|
|
|
trip-point@0 {
|
|
temperature = <0x11170>;
|
|
type = "passive";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x136>;
|
|
};
|
|
|
|
trip-point@1 {
|
|
temperature = <0x15f90>;
|
|
type = "passive";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x14>;
|
|
};
|
|
|
|
cpu_crit@0 {
|
|
temperature = <0x1adb0>;
|
|
type = "critical";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x137>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x14>;
|
|
cooling-device = <0x0d 0xffffffff 0xffffffff>;
|
|
contribution = <0x400>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu_thermal_zone {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x12 0x02>;
|
|
sustainable-power = <0x960>;
|
|
phandle = <0x138>;
|
|
|
|
trips {
|
|
phandle = <0x139>;
|
|
|
|
trip-point@0 {
|
|
temperature = <0xea60>;
|
|
type = "passive";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x13a>;
|
|
};
|
|
|
|
trip-point@1 {
|
|
temperature = <0x15f90>;
|
|
type = "passive";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x15>;
|
|
};
|
|
|
|
gpu_crit@0 {
|
|
temperature = <0x1adb0>;
|
|
type = "critical";
|
|
hysteresis = <0x00>;
|
|
phandle = <0x13b>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x15>;
|
|
cooling-device = <0x16 0xffffffff 0xffffffff>;
|
|
contribution = <0x400>;
|
|
};
|
|
};
|
|
};
|
|
|
|
npu_thermal_zone {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x12 0x03>;
|
|
};
|
|
|
|
ddr_thermal_zone {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x17 0x00>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
dcxo24M_clk {
|
|
#clock-cells = <0x00>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x16e3600>;
|
|
clock-output-names = "dcxo24M";
|
|
phandle = <0x22>;
|
|
};
|
|
|
|
rc16m_clk {
|
|
#clock-cells = <0x00>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0xf42400>;
|
|
clock-accuracy = <0x11e1a300>;
|
|
clock-output-names = "rc-16m";
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
ext32k_clk {
|
|
#clock-cells = <0x00>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x8000>;
|
|
clock-output-names = "ext-32k";
|
|
phandle = <0x13c>;
|
|
};
|
|
|
|
interrupt-controller@3400000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <0x03>;
|
|
#address-cells = <0x00>;
|
|
interrupt-controller;
|
|
reg = <0x00 0x3400000 0x00 0x10000 0x00 0x3460000 0x00 0xff004>;
|
|
interrupt-parent = <0x18>;
|
|
phandle = <0x18>;
|
|
};
|
|
|
|
interrupt-controller@0 {
|
|
compatible = "allwinner,sunxi-wakeupgen";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
#address-cells = <0x00>;
|
|
interrupt-parent = <0x18>;
|
|
phandle = <0x01>;
|
|
};
|
|
|
|
timer_arch {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
|
|
clock-frequency = <0x16e3600>;
|
|
interrupt-parent = <0x18>;
|
|
arm,no-tick-in-suspend;
|
|
};
|
|
|
|
power-management@7001400 {
|
|
compatible = "allwinner,a523-pmu\0syscon\0simple-mfd";
|
|
reg = <0x00 0x7001400 0x00 0x400>;
|
|
phandle = <0x13d>;
|
|
|
|
power-controller {
|
|
compatible = "allwinner,a523-power-controller";
|
|
clocks = <0x19 0x14>;
|
|
clock-names = "ppu";
|
|
resets = <0x19 0x0b>;
|
|
reset-names = "ppu_rst";
|
|
#power-domain-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x21>;
|
|
|
|
pd_dsp@0 {
|
|
reg = <0x00>;
|
|
};
|
|
|
|
pd_npu@1 {
|
|
reg = <0x01>;
|
|
};
|
|
|
|
pd_sram@3 {
|
|
reg = <0x03>;
|
|
};
|
|
|
|
pd_riscv@4 {
|
|
reg = <0x04>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pck-600@7060000 {
|
|
compatible = "allwinner,a523-pck\0syscon\0simple-mfd";
|
|
reg = <0x00 0x7060000 0x00 0x8000>;
|
|
phandle = <0x13e>;
|
|
|
|
power-controller {
|
|
compatible = "allwinner,a523-pck-600";
|
|
clocks = <0x19 0x15>;
|
|
clock-names = "pck";
|
|
resets = <0x19 0x0c>;
|
|
reset-names = "pck_rst";
|
|
#power-domain-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x1f>;
|
|
|
|
pd1_ve@0 {
|
|
reg = <0x00>;
|
|
};
|
|
|
|
pd1_vi@2 {
|
|
reg = <0x02>;
|
|
};
|
|
|
|
pd1_vo0@3 {
|
|
reg = <0x03>;
|
|
};
|
|
|
|
pd1_vo1@4 {
|
|
reg = <0x04>;
|
|
};
|
|
|
|
pd1_de@5 {
|
|
reg = <0x05>;
|
|
};
|
|
|
|
pd1_nand@6 {
|
|
reg = <0x06>;
|
|
};
|
|
|
|
pd1_pcie@7 {
|
|
reg = <0x07>;
|
|
};
|
|
};
|
|
};
|
|
|
|
intc-nmi@7010320 {
|
|
compatible = "allwinner,sun8i-nmi";
|
|
interrupt-parent = <0x18>;
|
|
#interrupt-cells = <0x02>;
|
|
#address-cells = <0x00>;
|
|
interrupt-controller;
|
|
reg = <0x00 0x7010320 0x00 0x0c>;
|
|
interrupts = <0x00 0x94 0x04>;
|
|
phandle = <0xd2>;
|
|
};
|
|
|
|
iommu@2010000 {
|
|
compatible = "allwinner,iommu-v15-sun55iw3";
|
|
reg = <0x00 0x2010000 0x00 0x1000>;
|
|
interrupts = <0x00 0x41 0x04>;
|
|
interrupt-names = "iommu-irq";
|
|
clocks = <0x1a 0x49>;
|
|
clock-names = "iommu";
|
|
#iommu-cells = <0x02>;
|
|
phandle = <0x1e>;
|
|
};
|
|
|
|
dram {
|
|
compatible = "allwinner,dram";
|
|
clocks = <0x1a 0x00>;
|
|
clock-names = "pll_ddr";
|
|
dram_para00 = <0x4b0>;
|
|
dram_para01 = <0x08>;
|
|
dram_para02 = <0x7070707>;
|
|
dram_para03 = <0xd0d0d0d>;
|
|
dram_para04 = <0xe0e>;
|
|
dram_para05 = <0x84848484>;
|
|
dram_para06 = <0x310a>;
|
|
dram_para07 = <0x10001000>;
|
|
dram_para08 = <0x00>;
|
|
dram_para09 = <0x54>;
|
|
dram_para10 = <0x2d>;
|
|
dram_para11 = <0x33>;
|
|
dram_para12 = <0x03>;
|
|
dram_para13 = <0x00>;
|
|
dram_para14 = <0x00>;
|
|
dram_para15 = <0x04>;
|
|
dram_para16 = <0x72>;
|
|
dram_para17 = <0x00>;
|
|
dram_para18 = <0x0c>;
|
|
dram_para19 = <0x00>;
|
|
dram_para20 = <0x00>;
|
|
dram_para21 = <0x26>;
|
|
dram_para22 = <0x80808080>;
|
|
dram_para23 = <0x6060606>;
|
|
dram_para24 = <0x5f090503>;
|
|
dram_para25 = <0x00>;
|
|
dram_para26 = <0x38000000>;
|
|
dram_para27 = <0x802f3333>;
|
|
dram_para28 = <0xc6c4c2c0>;
|
|
dram_para29 = <0x3a373233>;
|
|
dram_para30 = <0x6065>;
|
|
dram_para31 = <0x48484848>;
|
|
dram_para32 = <0x00>;
|
|
dram_para33 = <0x00>;
|
|
dram_para34 = <0x00>;
|
|
dram_para35 = <0x00>;
|
|
dram_para36 = <0x00>;
|
|
dram_para37 = <0x00>;
|
|
dram_para38 = <0x00>;
|
|
dram_para39 = <0x00>;
|
|
dram_para40 = <0x00>;
|
|
dram_para41 = <0x00>;
|
|
dram_para42 = <0x00>;
|
|
dram_para43 = <0x00>;
|
|
dram_para44 = <0x00>;
|
|
dram_para45 = <0x00>;
|
|
dram_para46 = <0x00>;
|
|
dram_para47 = <0x00>;
|
|
dram_para48 = <0x28282828>;
|
|
dram_para49 = <0x00>;
|
|
dram_para50 = <0x00>;
|
|
dram_para51 = <0x00>;
|
|
dram_para52 = <0x00>;
|
|
dram_para53 = <0x00>;
|
|
dram_para54 = <0x00>;
|
|
dram_para55 = <0x00>;
|
|
dram_para56 = <0xb2b4b0b2>;
|
|
dram_para57 = <0x00>;
|
|
dram_para58 = <0x00>;
|
|
dram_para59 = <0x00>;
|
|
dram_para60 = <0x00>;
|
|
dram_para61 = <0x00>;
|
|
dram_para62 = <0x00>;
|
|
dram_para63 = <0x00>;
|
|
dram_para64 = <0xc0c0c0c>;
|
|
dram_para65 = <0x00>;
|
|
dram_para66 = <0x00>;
|
|
dram_para67 = <0x00>;
|
|
dram_para68 = <0x00>;
|
|
dram_para69 = <0x00>;
|
|
dram_para70 = <0x00>;
|
|
dram_para71 = <0x00>;
|
|
dram_para72 = <0x9ea09ea0>;
|
|
dram_para73 = <0x00>;
|
|
dram_para74 = <0x00>;
|
|
dram_para75 = <0x00>;
|
|
dram_para76 = <0x00>;
|
|
dram_para77 = <0x00>;
|
|
dram_para78 = <0x00>;
|
|
dram_para79 = <0x00>;
|
|
dram_para80 = <0xc0c0c0c>;
|
|
dram_para81 = <0x00>;
|
|
dram_para82 = <0x00>;
|
|
dram_para83 = <0x00>;
|
|
dram_para84 = <0x00>;
|
|
dram_para85 = <0x00>;
|
|
dram_para86 = <0x00>;
|
|
dram_para87 = <0x00>;
|
|
dram_para88 = <0x96969696>;
|
|
dram_para89 = <0x00>;
|
|
dram_para90 = <0x00>;
|
|
dram_para91 = <0x00>;
|
|
dram_para92 = <0x00>;
|
|
dram_para93 = <0x00>;
|
|
dram_para94 = <0x00>;
|
|
dram_para95 = <0x00>;
|
|
phandle = <0x143>;
|
|
};
|
|
|
|
clk_ddr {
|
|
compatible = "allwinner,clock_ddr";
|
|
reg = <0x00 0x2001000 0x00 0x1000>;
|
|
clocks = <0x1a 0x00>;
|
|
clock-names = "pll_ddr";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x1b>;
|
|
};
|
|
|
|
opp_table {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0x1c>;
|
|
|
|
opp@150000000 {
|
|
opp-hz = <0x00 0x8f0d180>;
|
|
clock-latency-ns = <0x249f0>;
|
|
opp-microvolt = <0xdbba0>;
|
|
};
|
|
};
|
|
|
|
dmcfreq@3120000 {
|
|
compatible = "allwinner,sun55iw3-dmc\0syscon";
|
|
reg = <0x00 0x3120000 0x00 0x11000 0x00 0x2020000 0x00 0x4000>;
|
|
interrupts = <0x00 0x79 0x04>;
|
|
clocks = <0x1b 0x1a 0x32>;
|
|
clock-names = "dram\0bus";
|
|
operating-points-v2 = <0x1c>;
|
|
upthreshold = <0x3c>;
|
|
downdifferential = <0x14>;
|
|
vddcore-supply = <0x1d>;
|
|
normalvoltage = <0xdbba0>;
|
|
boostvoltage = <0xdbba0>;
|
|
phandle = <0x13f>;
|
|
};
|
|
|
|
soc@3000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
ranges;
|
|
phandle = <0x140>;
|
|
|
|
rt-media@1c0e000 {
|
|
compatible = "allwinner,rt-media";
|
|
};
|
|
|
|
ve@1c0e000 {
|
|
compatible = "allwinner,sunxi-cedar-ve";
|
|
reg = <0x00 0x1c0e000 0x00 0x1000 0x00 0x3000000 0x00 0x10>;
|
|
interrupts = <0x00 0x78 0x04>;
|
|
clocks = <0x1a 0x40 0x1a 0x3f 0x1a 0x58>;
|
|
clock-names = "bus_ve\0ve\0mbus_ve";
|
|
resets = <0x1a 0x08>;
|
|
reset-names = "reset_ve";
|
|
iommus = <0x1e 0x02 0x01>;
|
|
power-domains = <0x1f 0x00>;
|
|
ve-supply = <0x20>;
|
|
phandle = <0x141>;
|
|
};
|
|
|
|
ve1@1c0e000 {
|
|
compatible = "allwinner,sunxi-cedar-ve";
|
|
iommus = <0x1e 0x03 0x01>;
|
|
phandle = <0x142>;
|
|
};
|
|
|
|
pd-ve-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x1f 0x00>;
|
|
status = "okay";
|
|
phandle = <0x144>;
|
|
};
|
|
|
|
pd-vi-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x1f 0x02>;
|
|
status = "okay";
|
|
phandle = <0x145>;
|
|
};
|
|
|
|
pd-vo0-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x1f 0x03>;
|
|
status = "okay";
|
|
phandle = <0x146>;
|
|
};
|
|
|
|
pd-vo1-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x1f 0x04>;
|
|
status = "okay";
|
|
phandle = <0x147>;
|
|
};
|
|
|
|
pd-de-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x1f 0x05>;
|
|
status = "okay";
|
|
phandle = <0x148>;
|
|
};
|
|
|
|
pd-nand-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x1f 0x06>;
|
|
status = "okay";
|
|
phandle = <0x149>;
|
|
};
|
|
|
|
pd-pcie-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x1f 0x07>;
|
|
status = "okay";
|
|
phandle = <0x14a>;
|
|
};
|
|
|
|
pd-dsp-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x21 0x00>;
|
|
status = "okay";
|
|
phandle = <0x14b>;
|
|
};
|
|
|
|
pd-npu-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x21 0x01>;
|
|
status = "okay";
|
|
phandle = <0x14c>;
|
|
};
|
|
|
|
pd-sram-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x21 0x03>;
|
|
status = "okay";
|
|
phandle = <0x14d>;
|
|
};
|
|
|
|
pd-riscv-test@0 {
|
|
compatible = "allwinner,sunxi-power-domain-test";
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
power-domains = <0x21 0x04>;
|
|
status = "okay";
|
|
phandle = <0x14e>;
|
|
};
|
|
|
|
test_ccu@3000090 {
|
|
compatible = "allwinner,sun55iw3-test-ccu";
|
|
device_type = "ccu-test";
|
|
resets = <0x1a 0x17 0x1a 0x18>;
|
|
reset-names = "rst-uart7\0rst-uart6";
|
|
reg = <0x00 0x3000090 0x00 0x08>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x14f>;
|
|
};
|
|
|
|
rtc_ccu@7090000 {
|
|
compatible = "allwinner,sun55iw3-rtc-ccu";
|
|
reg = <0x00 0x7090000 0x00 0x400>;
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x23>;
|
|
};
|
|
|
|
clock@8817000 {
|
|
compatible = "allwinner,sun55iw3-cpupll";
|
|
reg = <0x00 0x8817000 0x00 0x4000>;
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
pll_step = <0x09>;
|
|
pll_ssc_scale = <0x0a>;
|
|
pll_ssc = <0x01>;
|
|
phandle = <0x04>;
|
|
};
|
|
|
|
ccu@2001000 {
|
|
compatible = "allwinner,sun55iw3-ccu";
|
|
reg = <0x00 0x2001000 0x00 0x1000>;
|
|
clocks = <0x22 0x23 0x04 0x24>;
|
|
clock-names = "hosc\0losc\0iosc";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x1a>;
|
|
};
|
|
|
|
r_ccu@7010000 {
|
|
compatible = "allwinner,sun55iw3-r-ccu";
|
|
reg = <0x00 0x7010000 0x00 0x230>;
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x19>;
|
|
};
|
|
|
|
mcu_ccu@7102000 {
|
|
compatible = "allwinner,sun55iw3-mcu-ccu";
|
|
reg = <0x00 0x7102000 0x00 0x165>;
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x78>;
|
|
};
|
|
|
|
sunxi-drm {
|
|
compatible = "allwinner,sunxi-drm";
|
|
fb_base = <0x00>;
|
|
status = "okay";
|
|
phandle = <0x150>;
|
|
};
|
|
|
|
de@5000000 {
|
|
compatible = "allwinner,display-engine-v350";
|
|
iommus = <0x1e 0x05 0x01>;
|
|
power-domains = <0x1f 0x05>;
|
|
reg = <0x00 0x5000000 0x00 0x400000>;
|
|
interrupts = <0x00 0x57 0x04>;
|
|
clocks = <0x1a 0x34 0x1a 0x35>;
|
|
clock-names = "clk_de\0clk_bus_de";
|
|
resets = <0x1a 0x02>;
|
|
reset-names = "rst_bus_de";
|
|
assigned-clocks = <0x1a 0x34>;
|
|
assigned-clock-parents = <0x1a 0x23>;
|
|
assigned-clock-rates = <0x23c34600>;
|
|
status = "okay";
|
|
chn_cfg_mode = <0x03>;
|
|
phandle = <0x151>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x152>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x25>;
|
|
phandle = <0x30>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x26>;
|
|
phandle = <0x36>;
|
|
};
|
|
|
|
endpoint@2 {
|
|
reg = <0x02>;
|
|
remote-endpoint = <0x27>;
|
|
phandle = <0x4e>;
|
|
};
|
|
|
|
endpoint@3 {
|
|
reg = <0x03>;
|
|
remote-endpoint = <0x28>;
|
|
phandle = <0x53>;
|
|
};
|
|
|
|
endpoint@4 {
|
|
reg = <0x04>;
|
|
remote-endpoint = <0x29>;
|
|
phandle = <0x3a>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x153>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x2a>;
|
|
phandle = <0x31>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x2b>;
|
|
phandle = <0x37>;
|
|
};
|
|
|
|
endpoint@2 {
|
|
reg = <0x02>;
|
|
remote-endpoint = <0x2c>;
|
|
phandle = <0x4f>;
|
|
};
|
|
|
|
endpoint@3 {
|
|
reg = <0x03>;
|
|
remote-endpoint = <0x2d>;
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
endpoint@4 {
|
|
reg = <0x04>;
|
|
remote-endpoint = <0x2e>;
|
|
phandle = <0x3b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vo0@5500000 {
|
|
compatible = "allwinner,tcon-top0";
|
|
power-domains = <0x1f 0x03>;
|
|
reg = <0x00 0x5500000 0x00 0xfff>;
|
|
clocks = <0x1a 0x95>;
|
|
clock-names = "clk_bus_dpss_top";
|
|
resets = <0x1a 0x3c>;
|
|
reset-names = "rst_bus_dpss_top";
|
|
status = "okay";
|
|
phandle = <0x2f>;
|
|
};
|
|
|
|
vo1@5730000 {
|
|
compatible = "allwinner,tcon-top1";
|
|
power-domains = <0x1f 0x04>;
|
|
reg = <0x00 0x5730000 0x00 0xfff>;
|
|
clocks = <0x1a 0x96>;
|
|
clock-names = "clk_bus_dpss_top";
|
|
resets = <0x1a 0x3d>;
|
|
reset-names = "rst_bus_dpss_top";
|
|
status = "disabled";
|
|
phandle = <0x39>;
|
|
};
|
|
|
|
tcon0@5501000 {
|
|
compatible = "allwinner,tcon-lcd";
|
|
reg = <0x00 0x5501000 0x00 0x1000>;
|
|
interrupts = <0x00 0x5a 0x04>;
|
|
clocks = <0x1a 0x9e 0x1a 0xa5>;
|
|
clock-names = "clk_tcon\0clk_bus_tcon";
|
|
resets = <0x1a 0x44>;
|
|
reset-names = "rst_bus_tcon";
|
|
top = <0x2f>;
|
|
status = "disabled";
|
|
phandle = <0x154>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x155>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x30>;
|
|
phandle = <0x25>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x31>;
|
|
phandle = <0x2a>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x01>;
|
|
phandle = <0x156>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x32>;
|
|
phandle = <0x40>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x33>;
|
|
phandle = <0x44>;
|
|
};
|
|
|
|
endpoint@2 {
|
|
reg = <0x02>;
|
|
remote-endpoint = <0x34>;
|
|
phandle = <0x48>;
|
|
};
|
|
|
|
endpoint@3 {
|
|
reg = <0x03>;
|
|
remote-endpoint = <0x35>;
|
|
phandle = <0x42>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tcon1@5502000 {
|
|
compatible = "allwinner,tcon-lcd";
|
|
reg = <0x00 0x5502000 0x00 0x1000>;
|
|
interrupts = <0x00 0x5c 0x04>;
|
|
clocks = <0x1a 0x9f 0x1a 0xa4>;
|
|
clock-names = "clk_tcon\0clk_bus_tcon";
|
|
resets = <0x1a 0x43>;
|
|
reset-names = "rst_bus_tcon";
|
|
top = <0x2f>;
|
|
status = "disabled";
|
|
phandle = <0x157>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x158>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x36>;
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x37>;
|
|
phandle = <0x2b>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x01>;
|
|
phandle = <0x159>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x38>;
|
|
phandle = <0x47>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tcon4@5731000 {
|
|
compatible = "allwinner,tcon-lcd";
|
|
reg = <0x00 0x5731000 0x00 0x1000>;
|
|
interrupts = <0x00 0x61 0x04>;
|
|
clocks = <0x1a 0xa0 0x1a 0xa3>;
|
|
clock-names = "clk_tcon\0clk_bus_tcon";
|
|
resets = <0x1a 0x42>;
|
|
reset-names = "rst_bus_tcon";
|
|
top = <0x39>;
|
|
status = "disabled";
|
|
phandle = <0x15a>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x15b>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x3a>;
|
|
phandle = <0x29>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x3b>;
|
|
phandle = <0x2e>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x01>;
|
|
phandle = <0x15c>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x3c>;
|
|
phandle = <0x41>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x3d>;
|
|
phandle = <0x43>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds0@0001000 {
|
|
compatible = "allwinner,lvds0";
|
|
resets = <0x1a 0x48>;
|
|
reset-names = "rst_bus_lvds";
|
|
phys = <0x3e 0x3f>;
|
|
phy-names = "combophy0\0combophy1";
|
|
status = "disabled";
|
|
phandle = <0x15d>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x15e>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x40>;
|
|
phandle = <0x32>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds1@0001000 {
|
|
compatible = "allwinner,lvds1";
|
|
reg = <0x00>;
|
|
resets = <0x1a 0x47>;
|
|
reset-names = "rst_bus_lvds";
|
|
status = "disabled";
|
|
phandle = <0x15f>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x160>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x41>;
|
|
phandle = <0x3c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rgb0@0001000 {
|
|
compatible = "allwinner,rgb0";
|
|
reg = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x161>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x162>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x42>;
|
|
phandle = <0x35>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rgb1@0001000 {
|
|
compatible = "allwinner,rgb1";
|
|
reg = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x163>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x164>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x43>;
|
|
phandle = <0x3d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
phy@5507000 {
|
|
compatible = "allwinner,sunxi-dsi-combo-phy0";
|
|
reg = <0x00 0x5507000 0x00 0x1ff>;
|
|
clocks = <0x1a 0x9d>;
|
|
clock-names = "phy_gating_clk";
|
|
resets = <0x1a 0x41>;
|
|
reset-names = "phy_rst_clk";
|
|
#clock-cells = <0x01>;
|
|
#phy-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x3e>;
|
|
};
|
|
|
|
dsi0@5506000 {
|
|
compatible = "allwinner,dsi0";
|
|
reg = <0x00 0x5506000 0x00 0xfff>;
|
|
interrupts = <0x00 0x5e 0x04>;
|
|
clocks = <0x1a 0x9a 0x1a 0x9d 0x3e 0x02 0x3e 0x01>;
|
|
clock-names = "dsi_clk\0dsi_gating_clk\0displl_hs\0displl_ls";
|
|
resets = <0x1a 0x41>;
|
|
reset-names = "dsi_rst_clk";
|
|
assigned-clocks = <0x1a 0x9a>;
|
|
assigned-clock-parents = <0x1a 0x0c>;
|
|
phys = <0x3e>;
|
|
phy-names = "combophy";
|
|
status = "disabled";
|
|
phandle = <0x165>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x166>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x44>;
|
|
phandle = <0x33>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
phy@5509000 {
|
|
compatible = "allwinner,sunxi-dsi-combo-phy1";
|
|
reg = <0x00 0x5509000 0x00 0x1ff>;
|
|
clocks = <0x1a 0x9c>;
|
|
clock-names = "phy_gating_clk";
|
|
resets = <0x1a 0x40>;
|
|
reset-names = "phy_rst_clk";
|
|
#clock-cells = <0x01>;
|
|
#phy-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x3f>;
|
|
};
|
|
|
|
dsi1@5508000 {
|
|
compatible = "allwinner,dsi1";
|
|
reg = <0x00 0x5508000 0x00 0xfff>;
|
|
interrupts = <0x00 0x5f 0x04>;
|
|
clocks = <0x1a 0x9b 0x1a 0x9c 0x3f 0x02 0x3f 0x01>;
|
|
clock-names = "dsi_clk\0dsi_gating_clk\0displl_hs\0displl_ls";
|
|
resets = <0x1a 0x40>;
|
|
reset-names = "dsi_rst_clk";
|
|
assigned-clocks = <0x1a 0x9b>;
|
|
assigned-clock-parents = <0x1a 0x0c>;
|
|
phys = <0x3f>;
|
|
phy-names = "combophy";
|
|
status = "disabled";
|
|
pinctrl-0 = <0x45>;
|
|
pinctrl-1 = <0x46>;
|
|
pinctrl-names = "active\0sleep";
|
|
phandle = <0x167>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x168>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x47>;
|
|
phandle = <0x38>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x48>;
|
|
phandle = <0x34>;
|
|
};
|
|
};
|
|
};
|
|
|
|
panel@0 {
|
|
compatible = "panel-dsi";
|
|
status = "disabled";
|
|
reg = <0x00>;
|
|
power0-supply = <0x49>;
|
|
power1-supply = <0x4a>;
|
|
enable0-gpios = <0x4b 0x04 0x0d 0x00>;
|
|
reset-gpios = <0x4b 0x04 0x0e 0x00>;
|
|
backlight = <0x4c>;
|
|
dsi,flags = <0x01>;
|
|
dsi,lanes = <0x04>;
|
|
dsi,format = <0x00>;
|
|
enable-delay-ms = <0x1f4>;
|
|
reset-delay-ms = <0x1f4>;
|
|
panel-init-sequence = [39 10 04 ff 98 81 03 39 10 02 01 00 39 10 02 02 00 39 10 02 03 53 39 10 02 04 d3 39 10 02 05 00 39 10 02 06 0d 39 10 02 07 08 39 10 02 08 00 39 10 02 09 00 39 10 02 0a 00 39 10 02 0b 00 39 10 02 0c 00 39 10 02 0d 00 39 10 02 0e 00 39 10 02 0f 28 39 10 02 10 28 39 10 02 11 00 39 10 02 12 00 39 10 02 13 00 39 10 02 14 00 39 10 02 15 00 39 10 02 16 00 39 10 02 17 00 39 10 02 18 00 39 10 02 19 00 39 10 02 1a 00 39 10 02 1b 00 39 10 02 1c 00 39 10 02 1d 00 39 10 02 1e 40 39 10 02 1f 80 39 10 02 20 06 39 10 02 21 01 39 10 02 22 00 39 10 02 23 00 39 10 02 24 00 39 10 02 25 00 39 10 02 26 00 39 10 02 27 00 39 10 02 28 33 39 10 02 29 33 39 10 02 2a 00 39 10 02 2b 00 39 10 02 2c 00 39 10 02 2d 00 39 10 02 2e 00 39 10 02 2f 00 39 10 02 30 00 39 10 02 31 00 39 10 02 32 00 39 10 02 33 00 39 10 02 34 03 39 10 02 35 00 39 10 02 36 00 39 10 02 37 00 39 10 02 38 96 39 10 02 39 00 39 10 02 3a 00 39 10 02 3b 00 39 10 02 3c 00 39 10 02 3d 00 39 10 02 3e 00 39 10 02 3f 00 39 10 02 40 00 39 10 02 41 00 39 10 02 42 00 39 10 02 43 00 39 10 02 44 00 39 10 02 50 00 39 10 02 51 23 39 10 02 52 45 39 10 02 53 67 39 10 02 54 89 39 10 02 55 ab 39 10 02 56 01 39 10 02 57 23 39 10 02 58 45 39 10 02 59 67 39 10 02 5a 89 39 10 02 5b ab 39 10 02 5c cd 39 10 02 5d ef 39 10 02 5e 00 39 10 02 5f 08 39 10 02 60 08 39 10 02 61 06 39 10 02 62 06 39 10 02 63 01 39 10 02 64 01 39 10 02 65 00 39 10 02 66 00 39 10 02 67 02 39 10 02 68 15 39 10 02 69 15 39 10 02 6a 14 39 10 02 6b 14 39 10 02 6c 0d 39 10 02 6d 0d 39 10 02 6e 0c 39 10 02 6f 0c 39 10 02 70 0f 39 10 02 71 0f 39 10 02 72 0e 39 10 02 73 0e 39 10 02 74 02 39 10 02 75 08 39 10 02 76 08 39 10 02 77 06 39 10 02 78 06 39 10 02 79 01 39 10 02 7a 01 39 10 02 7b 00 39 10 02 7c 00 39 10 02 7d 02 39 10 02 7e 15 39 10 02 7f 15 39 10 02 80 14 39 10 02 81 14 39 10 02 82 0d 39 10 02 83 0d 39 10 02 84 0c 39 10 02 85 0c 39 10 02 86 0f 39 10 02 87 0f 39 10 02 88 0e 39 10 02 89 0e 39 10 02 8a 02 39 10 04 ff 98 81 04 39 10 02 6e 2b 39 10 02 6f 37 39 10 02 3a a4 39 10 02 8d 1a 39 10 02 87 ba 39 10 02 b2 d1 39 10 02 88 0b 39 10 02 38 01 39 10 02 39 00 39 10 02 b5 07 39 10 02 31 75 39 10 02 3b 98 39 10 04 ff 98 81 01 39 10 02 43 33 39 10 02 22 0a 39 10 02 31 00 39 10 02 53 48 39 10 02 55 48 39 10 02 50 99 39 10 02 51 94 39 10 02 60 10 39 10 02 62 20 39 10 02 a0 00 39 10 02 a1 00 39 10 02 a2 15 39 10 02 a3 14 39 10 02 a4 1b 39 10 02 a5 2f 39 10 02 a6 25 39 10 02 a7 24 39 10 02 a8 80 39 10 02 a9 1f 39 10 02 aa 2c 39 10 02 ab 6c 39 10 02 ac 16 39 10 02 ad 14 39 10 02 ae 4d 39 10 02 af 20 39 10 02 b0 29 39 10 02 b1 4f 39 10 02 b2 5f 39 10 02 b3 23 39 10 02 c0 00 39 10 02 c1 2e 39 10 02 c2 3b 39 10 02 c3 15 39 10 02 c4 16 39 10 02 c5 28 39 10 02 c6 1a 39 10 02 c7 1c 39 10 02 c8 a7 39 10 02 c9 1b 39 10 02 ca 28 39 10 02 cb 92 39 10 02 cc 1f 39 10 02 cd 1c 39 10 02 ce 4b 39 10 02 cf 1f 39 10 02 d0 28 39 10 02 d1 4e 39 10 02 d2 5c 39 10 02 d3 23 39 10 04 ff 98 81 00 39 10 02 11 00 39 78 02 29 00 39 10 02 35 00];
|
|
panel-exit-sequence = <0x5140128 0x5500110>;
|
|
phandle = <0x169>;
|
|
|
|
display-timings {
|
|
native-mode = <0x4d>;
|
|
|
|
timing0 {
|
|
clock-frequency = <0x410e1a0>;
|
|
hback-porch = <0x14>;
|
|
hactive = <0x320>;
|
|
hfront-porch = <0x14>;
|
|
hsync-len = <0x14>;
|
|
vback-porch = <0x08>;
|
|
vactive = <0x500>;
|
|
vfront-porch = <0x1e>;
|
|
vsync-len = <0x04>;
|
|
phandle = <0x4d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tcon2@5503000 {
|
|
compatible = "allwinner,tcon-tv";
|
|
reg = <0x00 0x5503000 0x00 0x1000>;
|
|
interrupts = <0x00 0x5b 0x04>;
|
|
clocks = <0x1a 0xa6 0x1a 0xa9>;
|
|
clock-names = "clk_tcon\0clk_bus_tcon";
|
|
resets = <0x1a 0x46>;
|
|
reset-names = "rst_bus_tcon";
|
|
top = <0x2f>;
|
|
status = "okay";
|
|
phandle = <0x16a>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x16b>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x4e>;
|
|
phandle = <0x27>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x4f>;
|
|
phandle = <0x2c>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x01>;
|
|
phandle = <0x16c>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x50>;
|
|
phandle = <0x52>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi@5520000 {
|
|
compatible = "allwinner,sunxi-hdmi";
|
|
reg = <0x00 0x5520000 0x00 0x100000>;
|
|
interrupts = <0x00 0x5d 0x04>;
|
|
clocks = <0x1a 0x99 0x1a 0x97 0x1a 0x98 0x1a 0xa6>;
|
|
clock-names = "clk_hdmi\0clk_hdmi_24M\0clk_cec\0clk_tcon_tv";
|
|
resets = <0x1a 0x3e 0x1a 0x3f>;
|
|
reset-names = "rst_bus_sub\0rst_bus_main";
|
|
assigned-clocks = <0x1a 0x99>;
|
|
assigned-clock-rates = <0x00 0x00>;
|
|
power-domains = <0x1f 0x03>;
|
|
status = "okay";
|
|
hdmi_used = <0x01>;
|
|
cldo1-supply = <0x4a>;
|
|
hdmi_power0 = "cldo1";
|
|
vmid-supply = <0x51>;
|
|
hdmi_power1 = "vmid";
|
|
hdmi_power_cnt = <0x02>;
|
|
hdmi_hdcp_enable = <0x01>;
|
|
hdmi_hdcp22_enable = <0x00>;
|
|
hdmi_cts_compatibility = <0x00>;
|
|
hdmi_cec_support = <0x01>;
|
|
hdmi_cec_super_standby = <0x01>;
|
|
hdmi_skip_bootedid = <0x01>;
|
|
ddc_en_io_ctrl = <0x00>;
|
|
power_io_ctrl = <0x00>;
|
|
phandle = <0x16d>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x16e>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x52>;
|
|
phandle = <0x50>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tcon3@5504000 {
|
|
compatible = "allwinner,tcon-tv";
|
|
reg = <0x00 0x5504000 0x00 0x1000>;
|
|
interrupts = <0x00 0x60 0x04>;
|
|
clocks = <0x1a 0xa7 0x1a 0xa8>;
|
|
clock-names = "clk_tcon\0clk_bus_tcon";
|
|
resets = <0x1a 0x45>;
|
|
reset-names = "rst_bus_tcon";
|
|
top = <0x2f>;
|
|
status = "disabled";
|
|
phandle = <0x16f>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x170>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x53>;
|
|
phandle = <0x28>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x54>;
|
|
phandle = <0x2d>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x01>;
|
|
phandle = <0x171>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x55>;
|
|
phandle = <0x58>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
drm_edp@5720000 {
|
|
compatible = "allwinner,drm-edp";
|
|
reg = <0x00 0x5720000 0x00 0x4000>;
|
|
interrupts = <0x00 0x90 0x04>;
|
|
power-domains = <0x1f 0x03>;
|
|
clocks = <0x1a 0xab 0x1a 0xaa 0x1a 0x97>;
|
|
clock-names = "clk_bus_edp\0clk_edp\0clk_24m_edp";
|
|
resets = <0x1a 0x49>;
|
|
reset-names = "rst_bus_edp";
|
|
assigned-clocks = <0x1a 0xaa>;
|
|
assigned-clock-parents = <0x1a 0x1d>;
|
|
status = "disabled";
|
|
edp_ssc_en = <0x00>;
|
|
edp_ssc_mode = <0x00>;
|
|
edp_psr_support = <0x00>;
|
|
edp_colordepth = <0x08>;
|
|
edp_color_fmt = <0x00>;
|
|
lane1_sw = <0x00>;
|
|
lane1_pre = <0x00>;
|
|
lane2_sw = <0x00>;
|
|
lane2_pre = <0x00>;
|
|
lane3_sw = <0x00>;
|
|
lane3_pre = <0x00>;
|
|
efficient_training = <0x00>;
|
|
sink_capacity_prefer = <0x01>;
|
|
edid_timings_prefer = <0x01>;
|
|
timings_fixed = <0x01>;
|
|
vcc-edp-supply = <0x56>;
|
|
vdd-edp-supply = <0x20>;
|
|
panel = <0x57>;
|
|
phandle = <0x172>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x173>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x58>;
|
|
phandle = <0x55>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x01>;
|
|
phandle = <0x174>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x59>;
|
|
phandle = <0x12a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
disp@5000000 {
|
|
compatible = "allwinner,sunxi-disp";
|
|
reg = <0x00 0x5000000 0x00 0x400000 0x00 0x5500000 0x00 0x1000 0x00 0x5501000 0x00 0x1000 0x00 0x5502000 0x00 0x1000 0x00 0x5503000 0x00 0x1000 0x00 0x5504000 0x00 0x1000 0x00 0x5731000 0x00 0x1000 0x00 0x5506000 0x00 0x1fff 0x00 0x5508000 0x00 0x1fff>;
|
|
interrupts = <0x00 0x57 0x04 0x00 0x5a 0x04 0x00 0x5c 0x04 0x00 0x5b 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x5e 0x04 0x00 0x5f 0x04>;
|
|
clocks = <0x1a 0x34 0x1a 0x34 0x1a 0x35 0x1a 0x35 0x1a 0x9e 0x1a 0x9f 0x1a 0xa6 0x1a 0xa7 0x1a 0xa0 0x1a 0xa5 0x1a 0xa4 0x1a 0xa9 0x1a 0xa8 0x1a 0xa3 0x1a 0x95 0x1a 0x95 0x1a 0x95 0x1a 0x95 0x1a 0x96 0x1a 0x9a 0x1a 0x9b 0x1a 0x9d 0x1a 0x9c 0x1a 0xa1 0x1a 0xa2>;
|
|
clock-names = "clk_de0\0clk_de1\0clk_bus_de0\0clk_bus_de1\0clk_tcon0\0clk_tcon1\0clk_tcon2\0clk_tcon3\0clk_tcon4\0clk_bus_tcon0\0clk_bus_tcon1\0clk_bus_tcon2\0clk_bus_tcon3\0clk_bus_tcon4\0clk_bus_dpss_top0\0clk_bus_dpss_top1\0clk_bus_dpss_top2\0clk_bus_dpss_top3\0clk_bus_dpss_top4\0clk_mipi_dsi0\0clk_mipi_dsi1\0clk_bus_mipi_dsi0\0clk_bus_mipi_dsi1\0clk_mipi_dsi_combphy0\0clk_mipi_dsi_combphy1";
|
|
resets = <0x1a 0x02 0x1a 0x02 0x1a 0x44 0x1a 0x43 0x1a 0x46 0x1a 0x45 0x1a 0x42 0x1a 0x48 0x1a 0x47 0x1a 0x3c 0x1a 0x3c 0x1a 0x3c 0x1a 0x3c 0x1a 0x3d 0x1a 0x41 0x1a 0x40>;
|
|
reset-names = "rst_bus_de0\0rst_bus_de1\0rst_bus_tcon0\0rst_bus_tcon1\0rst_bus_tcon2\0rst_bus_tcon3\0rst_bus_tcon4\0rst_bus_lvds0\0rst_bus_lvds1\0rst_bus_dpss_top0\0rst_bus_dpss_top1\0rst_bus_dpss_top2\0rst_bus_dpss_top3\0rst_bus_dpss_top4\0rst_bus_mipi_dsi0\0rst_bus_mipi_dsi1";
|
|
assigned-clocks = <0x1a 0x34 0x1a 0x9e 0x1a 0x9f 0x1a 0xa0 0x1a 0xa9 0x1a 0xa6 0x1a 0xa7 0x1a 0x9a 0x1a 0x9b 0x1a 0xa1 0x1a 0xa2>;
|
|
assigned-clock-parents = <0x1a 0x23 0x1a 0x1a 0x1a 0x1a 0x1a 0x1a 0x1a 0x1a 0x1a 0x1d 0x1a 0x1d 0x1a 0x0c 0x1a 0x0c 0x1a 0x1a 0x1a 0x1a>;
|
|
assigned-clock-rates = <0x23c34600>;
|
|
iommus = <0x1e 0x05 0x00>;
|
|
power-domains = <0x1f 0x05 0x1f 0x03>;
|
|
power-domain-names = "pd_de\0pd_vo0";
|
|
status = "okay";
|
|
boot_disp = <0x00>;
|
|
fb_base = <0x00>;
|
|
disp_init_enable = <0x01>;
|
|
disp_mode = <0x00>;
|
|
screen0_output_type = <0x01>;
|
|
screen0_output_mode = <0x04>;
|
|
screen0_to_lcd_index = <0x01>;
|
|
screen1_output_type = <0x03>;
|
|
screen1_output_mode = <0x0a>;
|
|
screen1_output_format = <0x00>;
|
|
screen1_output_bits = <0x00>;
|
|
screen1_output_eotf = <0x04>;
|
|
screen1_output_cs = <0x101>;
|
|
screen1_output_dvi_hdmi = <0x02>;
|
|
screen1_output_range = <0x02>;
|
|
screen1_output_scan = <0x00>;
|
|
screen1_output_aspect_ratio = <0x08>;
|
|
screen1_to_lcd_index = <0x02>;
|
|
dev0_output_type = <0x01>;
|
|
dev0_output_mode = <0x04>;
|
|
dev0_screen_id = <0x00>;
|
|
dev0_do_hpd = <0x00>;
|
|
dev1_output_type = <0x04>;
|
|
dev1_output_mode = <0x0a>;
|
|
dev1_screen_id = <0x01>;
|
|
dev1_do_hpd = <0x01>;
|
|
def_output_dev = <0x00>;
|
|
hdmi_mode_check = <0x01>;
|
|
fb_format = <0x00>;
|
|
fb_num = <0x01>;
|
|
fb_debug = <0x01>;
|
|
fb0_map = <0x00 0x01 0x00 0x10>;
|
|
fb0_width = <0x320>;
|
|
fb0_height = <0x500>;
|
|
fb1_map = <0x00 0x02 0x00 0x10>;
|
|
fb1_width = <0x12c>;
|
|
fb1_height = <0x12c>;
|
|
fb2_map = <0x01 0x00 0x00 0x10>;
|
|
fb2_width = <0x500>;
|
|
fb2_height = <0x2d0>;
|
|
fb3_map = <0x01 0x01 0x00 0x10>;
|
|
fb3_width = <0x12c>;
|
|
fb3_height = <0x12c>;
|
|
chn_cfg_mode = <0x03>;
|
|
disp_para_zone = <0x01>;
|
|
cldo4-supply = <0x49>;
|
|
cldo1-supply = <0x4a>;
|
|
phandle = <0x175>;
|
|
};
|
|
|
|
edp0@5720000 {
|
|
compatible = "allwinner,sunxi-edp0";
|
|
reg = <0x00 0x5720000 0x00 0x4000>;
|
|
interrupts = <0x00 0x90 0x04>;
|
|
clocks = <0x1a 0xab 0x1a 0xaa 0x1a 0x97>;
|
|
clock-names = "clk_bus_edp\0clk_edp\0edp_clk_24m";
|
|
resets = <0x1a 0x49>;
|
|
reset-names = "rst_bus_edp";
|
|
assigned-clocks = <0x1a 0xaa>;
|
|
assigned-clock-parents = <0x1a 0x1d>;
|
|
status = "disabled";
|
|
phandle = <0x176>;
|
|
};
|
|
|
|
lcd0@1c0c000 {
|
|
compatible = "allwinner,sunxi-lcd0";
|
|
reg = <0x00 0x1c0c000 0x00 0x00>;
|
|
pinctrl-names = "active\0sleep";
|
|
lcd_used = <0x01>;
|
|
status = "okay";
|
|
lcd_driver_name = "SQ101D_Q5DI404_84H501";
|
|
lcd_backlight = <0x32>;
|
|
lcd_if = <0x04>;
|
|
lcd_x = <0x4b0>;
|
|
lcd_y = <0x780>;
|
|
lcd_width = <0x88>;
|
|
lcd_height = <0xd9>;
|
|
lcd_dclk_freq = <0x9d>;
|
|
lcd_pwm_used = <0x00>;
|
|
lcd_pwm_ch = <0x07>;
|
|
lcd_pwm_freq = <0xc350>;
|
|
lcd_pwm_pol = <0x00>;
|
|
lcd_pwm_max_limit = <0xff>;
|
|
lcd_hbp = <0x32>;
|
|
lcd_ht = <0x532>;
|
|
lcd_hspw = <0x0a>;
|
|
lcd_vbp = <0x14>;
|
|
lcd_vt = <0x7a8>;
|
|
lcd_vspw = <0x04>;
|
|
lcd_frm = <0x00>;
|
|
lcd_gamma_en = <0x00>;
|
|
lcd_bright_curve_en = <0x00>;
|
|
lcd_cmap_en = <0x00>;
|
|
deu_mode = <0x00>;
|
|
lcdgamma4iep = <0x16>;
|
|
smart_color = <0x5a>;
|
|
lcd_dsi_if = <0x00>;
|
|
lcd_dsi_lane = <0x04>;
|
|
lcd_dsi_format = <0x00>;
|
|
lcd_dsi_te = <0x00>;
|
|
lcd_dsi_eotp = <0x00>;
|
|
lcd_power1 = "cldo4";
|
|
lcd_power2 = "cldo1";
|
|
lcd_gpio_2 = <0x4b 0x03 0x16 0x00>;
|
|
pinctrl-0 = <0x5a>;
|
|
pinctrl-1 = <0x5b>;
|
|
lcd_bl_0_percent = <0x05>;
|
|
lcd_bl_100_percent = <0x5a>;
|
|
phandle = <0x177>;
|
|
};
|
|
|
|
lcd1@1c0c000 {
|
|
compatible = "allwinner,sunxi-lcd1";
|
|
reg = <0x00 0x1c0c000 0x00 0x00>;
|
|
pinctrl-names = "active\0sleep";
|
|
lcd_used = <0x01>;
|
|
lcd_driver_name = "CC10132007_40A";
|
|
lcd_backlight = <0x32>;
|
|
lcd_if = <0x04>;
|
|
lcd_x = <0x320>;
|
|
lcd_y = <0x500>;
|
|
lcd_width = <0x87>;
|
|
lcd_height = <0xd8>;
|
|
lcd_dclk_freq = <0x44>;
|
|
lcd_pwm_used = <0x01>;
|
|
lcd_pwm_ch = <0x00>;
|
|
lcd_pwm_freq = <0xc350>;
|
|
lcd_pwm_pol = <0x00>;
|
|
lcd_pwm_max_limit = <0xff>;
|
|
lcd_pwm_name = "backlight";
|
|
lcd_hbp = <0x28>;
|
|
lcd_ht = <0x35c>;
|
|
lcd_hspw = <0x14>;
|
|
lcd_vbp = <0x0c>;
|
|
lcd_vt = <0x52a>;
|
|
lcd_vspw = <0x04>;
|
|
lcd_frm = <0x00>;
|
|
lcd_gamma_en = <0x00>;
|
|
lcd_bright_curve_en = <0x00>;
|
|
lcd_cmap_en = <0x00>;
|
|
lcd_start_delay = <0x01>;
|
|
lcd_dsi_if = <0x00>;
|
|
lcd_dsi_lane = <0x04>;
|
|
lcd_dsi_format = <0x00>;
|
|
lcd_dsi_te = <0x00>;
|
|
lcd_dsi_eotp = <0x00>;
|
|
deu_mode = <0x00>;
|
|
lcdgamma4iep = <0x16>;
|
|
smart_color = <0x5a>;
|
|
lcd_power1 = "cldo4";
|
|
lcd_power2 = "cldo1";
|
|
lcd_gpio_2 = <0x4b 0x03 0x16 0x00>;
|
|
pinctrl-0 = <0x45>;
|
|
pinctrl-1 = <0x46>;
|
|
lcd_bl_en = <0x4b 0x07 0x12 0x00>;
|
|
lcd_bl_0_percent = <0x05>;
|
|
phandle = <0x178>;
|
|
};
|
|
|
|
lcd2@1c0c000 {
|
|
compatible = "allwinner,sunxi-lcd2";
|
|
reg = <0x00 0x1c0c000 0x00 0x00>;
|
|
pinctrl-names = "active\0sleep";
|
|
lcd_used = <0x01>;
|
|
lcd_driver_name = "default_lcd";
|
|
lcd_backlight = <0x32>;
|
|
lcd_if = <0x00>;
|
|
lcd_x = <0x320>;
|
|
lcd_y = <0x1e0>;
|
|
lcd_width = <0x96>;
|
|
lcd_height = <0x5e>;
|
|
lcd_dclk_freq = <0x30>;
|
|
lcd_pwm_used = <0x01>;
|
|
lcd_pwm_ch = <0x07>;
|
|
lcd_pwm_freq = <0xc350>;
|
|
lcd_pwm_pol = <0x00>;
|
|
lcd_hbp = <0x37>;
|
|
lcd_ht = <0x4d8>;
|
|
lcd_hspw = <0x14>;
|
|
lcd_vbp = <0x23>;
|
|
lcd_vt = <0x28a>;
|
|
lcd_vspw = <0x0a>;
|
|
lcd_lvds_if = <0x00>;
|
|
lcd_lvds_colordepth = <0x01>;
|
|
lcd_lvds_mode = <0x00>;
|
|
lcd_frm = <0x01>;
|
|
lcd_io_phase = <0x00>;
|
|
lcd_gamma_en = <0x00>;
|
|
lcd_bright_curve_en = <0x00>;
|
|
lcd_cmap_en = <0x00>;
|
|
deu_mode = <0x00>;
|
|
lcdgamma4iep = <0x16>;
|
|
smart_color = <0x5a>;
|
|
pinctrl-0 = <0x5c>;
|
|
pinctrl-1 = <0x5d>;
|
|
phandle = <0x179>;
|
|
};
|
|
|
|
pinctrl@7022000 {
|
|
#address-cells = <0x01>;
|
|
compatible = "allwinner,sun55iw3-r-pinctrl";
|
|
reg = <0x00 0x7022000 0x00 0x800 0x00 0x7010374 0x00 0x04 0x00 0x7010378 0x00 0x04>;
|
|
reg-names = "r-pio\0i2s0\0dmic";
|
|
interrupts = <0x00 0x9f 0x04 0x00 0xa1 0x04>;
|
|
clocks = <0x1a 0x02 0x22 0x23 0x04>;
|
|
clock-names = "apb\0hosc\0losc";
|
|
gpio-controller;
|
|
#gpio-cells = <0x03>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
phandle = <0x62>;
|
|
|
|
uart8_pins@0 {
|
|
pins = "PL2\0PL3";
|
|
function = "s_uart0";
|
|
phandle = <0x74>;
|
|
};
|
|
|
|
uart8_pins@1 {
|
|
pins = "PL2\0PL3";
|
|
function = "gpio_in";
|
|
phandle = <0x75>;
|
|
};
|
|
|
|
uart9_pins@0 {
|
|
pins = "PM0\0PM1";
|
|
function = "s_uart1";
|
|
phandle = <0x76>;
|
|
};
|
|
|
|
uart9_pins@1 {
|
|
pins = "PM0\0PM1";
|
|
function = "gpio_in";
|
|
phandle = <0x77>;
|
|
};
|
|
|
|
s_twi0@0 {
|
|
pins = "PL0\0PL1";
|
|
function = "s_twi0";
|
|
drive-strength = <0x0a>;
|
|
bias-pull-up;
|
|
phandle = <0xcc>;
|
|
};
|
|
|
|
s_twi0@1 {
|
|
pins = "PL0\0PL1";
|
|
function = "gpio_in";
|
|
phandle = <0xcd>;
|
|
};
|
|
|
|
s_irrx@0 {
|
|
pins = "PL11";
|
|
function = "s_cir";
|
|
phandle = <0xbd>;
|
|
};
|
|
|
|
s_irrx@1 {
|
|
pins = "PL11";
|
|
function = "gpio_in";
|
|
phandle = <0xbe>;
|
|
};
|
|
};
|
|
|
|
g2d@5440000 {
|
|
compatible = "allwinner,sunxi-g2d";
|
|
reg = <0x00 0x5440000 0x00 0x30000>;
|
|
interrupts = <0x00 0x8f 0x04>;
|
|
clocks = <0x1a 0x39 0x1a 0x38>;
|
|
clock-names = "bus\0g2d";
|
|
resets = <0x1a 0x04>;
|
|
iommus = <0x1e 0x04 0x01>;
|
|
power-domains = <0x1f 0x03>;
|
|
power-domain-names = "pd1_vo0";
|
|
assigned-clocks = <0x1a 0x38>;
|
|
assigned-clock-rates = <0x11e1a300>;
|
|
phandle = <0x17a>;
|
|
};
|
|
|
|
pinctrl@2000000 {
|
|
#address-cells = <0x01>;
|
|
compatible = "allwinner,sun55iw3-pinctrl";
|
|
reg = <0x00 0x2000000 0x00 0x800 0x00 0x7010374 0x00 0x04 0x00 0x7010378 0x00 0x04>;
|
|
reg-names = "pio\0i2s0\0dmic";
|
|
interrupts = <0x00 0x45 0x04 0x00 0x47 0x04 0x00 0x49 0x04 0x00 0x4b 0x04 0x00 0x4d 0x04 0x00 0x4f 0x04 0x00 0x51 0x04 0x00 0x53 0x04 0x00 0x55 0x04 0x00 0x8c 0x04>;
|
|
clocks = <0x1a 0x30 0x22 0x23 0x04>;
|
|
clock-names = "apb\0hosc\0losc";
|
|
gpio-controller;
|
|
#gpio-cells = <0x03>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
vcc-pg-supply = <0x5e>;
|
|
vcc-pc-supply = <0x5e>;
|
|
vcc-pf-supply = <0x5e>;
|
|
vcc-pfo-supply = <0x5f>;
|
|
phandle = <0x4b>;
|
|
|
|
sdc0@0 {
|
|
pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
|
|
function = "sdc0";
|
|
drive-strength = <0x28>;
|
|
bias-pull-up;
|
|
power-source = <0xce4>;
|
|
phandle = <0xed>;
|
|
};
|
|
|
|
sdc0@1 {
|
|
pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
|
|
function = "sdc0";
|
|
drive-strength = <0x28>;
|
|
bias-pull-up;
|
|
power-source = <0x708>;
|
|
phandle = <0xee>;
|
|
};
|
|
|
|
sdc0@2 {
|
|
pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
|
|
function = "gpio_in";
|
|
power-source = <0xce4>;
|
|
phandle = <0xef>;
|
|
};
|
|
|
|
sdc0@3 {
|
|
pins = "PF2\0PF4";
|
|
function = "uart0";
|
|
drive-strength = <0x0a>;
|
|
bias-pull-up;
|
|
power-source = <0xce4>;
|
|
phandle = <0xf0>;
|
|
};
|
|
|
|
sdc0@4 {
|
|
pins = "PF0\0PF1\0PF3\0PF5";
|
|
function = "jtag";
|
|
drive-strength = <0x0a>;
|
|
bias-pull-up;
|
|
power-source = <0xce4>;
|
|
phandle = <0xf1>;
|
|
};
|
|
|
|
sdc1@0 {
|
|
pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
|
|
function = "sdc1";
|
|
drive-strength = <0x28>;
|
|
bias-pull-up;
|
|
phandle = <0xf2>;
|
|
};
|
|
|
|
sdc1@1 {
|
|
pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
|
|
function = "gpio_in";
|
|
phandle = <0xf3>;
|
|
};
|
|
|
|
sdc2@0 {
|
|
pins = "PC1\0PC5\0PC6\0PC8\0PC9\0PC10\0PC11\0PC13\0PC14\0PC15\0PC16";
|
|
function = "sdc2";
|
|
drive-strength = <0x28>;
|
|
bias-pull-up;
|
|
phandle = <0xea>;
|
|
};
|
|
|
|
sdc2@1 {
|
|
pins = "PC0\0PC1\0PC5\0PC6\0PC8\0PC9\0PC10\0PC11\0PC13\0PC14\0PC15\0PC16";
|
|
function = "gpio_in";
|
|
phandle = <0xec>;
|
|
};
|
|
|
|
sdc2@2 {
|
|
pins = "PC0";
|
|
function = "sdc2";
|
|
drive-strength = <0x28>;
|
|
bias-pull-down;
|
|
phandle = <0xeb>;
|
|
};
|
|
|
|
uart1@0 {
|
|
pins = "PG6\0PG7\0PG8\0PG9";
|
|
function = "uart1";
|
|
drive-strength = <0x0a>;
|
|
bias-pull-up;
|
|
phandle = <0x66>;
|
|
};
|
|
|
|
uart1@1 {
|
|
pins = "PG6\0PG7\0PG8\0PG9";
|
|
function = "gpio_in";
|
|
phandle = <0x67>;
|
|
};
|
|
|
|
dsi0_4lane@0 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9";
|
|
function = "dsi0";
|
|
drive-strength = <0x1e>;
|
|
bias-disable;
|
|
phandle = <0x5a>;
|
|
};
|
|
|
|
dsi0_4lane@1 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9";
|
|
function = "io_disabled";
|
|
bias-disable;
|
|
phandle = <0x5b>;
|
|
};
|
|
|
|
dsi1_4lane@0 {
|
|
pins = "PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19";
|
|
function = "dsi1";
|
|
drive-strength = <0x1e>;
|
|
bias-disable;
|
|
phandle = <0x45>;
|
|
};
|
|
|
|
dsi1_4lane@1 {
|
|
pins = "PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19";
|
|
function = "io_disabled";
|
|
bias-disable;
|
|
phandle = <0x46>;
|
|
};
|
|
|
|
rgb18@0 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
|
|
function = "lcd0";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x17b>;
|
|
};
|
|
|
|
rgb18@1 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
|
|
function = "gpio_in";
|
|
phandle = <0x17c>;
|
|
};
|
|
|
|
lvds0@0 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9";
|
|
function = "lvds";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x17d>;
|
|
};
|
|
|
|
lvds0@1 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9";
|
|
function = "gpio_in";
|
|
phandle = <0x17e>;
|
|
};
|
|
|
|
lvds1@0 {
|
|
pins = "PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19";
|
|
function = "lvds1";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x17f>;
|
|
};
|
|
|
|
lvds1@1 {
|
|
pins = "PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19";
|
|
function = "gpio_in";
|
|
phandle = <0x180>;
|
|
};
|
|
|
|
lvds2@0 {
|
|
pins = "PJ0\0PJ1\0PJ2\0PJ3\0PJ4\0PJ5\0PJ6\0PJ7\0PJ8\0PJ9";
|
|
function = "lvds2";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x181>;
|
|
};
|
|
|
|
lvds2@1 {
|
|
pins = "PJ0\0PJ1\0PJ2\0PJ3\0PJ4\0PJ5\0PJ6\0PJ7\0PJ8\0PJ9";
|
|
function = "gpio_in";
|
|
phandle = <0x182>;
|
|
};
|
|
|
|
lvds3@0 {
|
|
pins = "PJ10\0PJ11\0PJ12\0PJ13\0PJ14\0PJ15\0PJ16\0PJ17\0PJ18\0PJ19";
|
|
function = "lvds3";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x183>;
|
|
};
|
|
|
|
lvds3@1 {
|
|
pins = "PJ10\0PJ11\0PJ12\0PJ13\0PJ14\0PJ15\0PJ16\0PJ17\0PJ18\0PJ19";
|
|
function = "gpio_in";
|
|
phandle = <0x184>;
|
|
};
|
|
|
|
rgb1@0 {
|
|
pins = "PJ0\0PJ1\0PJ2\0PJ3\0PJ4\0PJ5\0PJ6\0PJ7\0PJ8\0PJ9\0PJ10\0PJ11\0PJ12\0PJ13\0PJ14\0PJ15\0PJ16\0PJ17\0PJ18\0PJ19\0PJ20\0PJ21\0PJ22\0PJ23\0PJ24\0PJ25\0PJ26\0PJ27";
|
|
function = "lcd1";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x185>;
|
|
};
|
|
|
|
rgb1@1 {
|
|
pins = "PJ0\0PJ1\0PJ2\0PJ3\0PJ4\0PJ5\0PJ6\0PJ7\0PJ8\0PJ9\0PJ10\0PJ11\0PJ12\0PJ13\0PJ14\0PJ15\0PJ16\0PJ17\0PJ18\0PJ19\0PJ20\0PJ21\0PJ22\0PJ23\0PJ24\0PJ25\0PJ26\0PJ27";
|
|
function = "gpio_in";
|
|
phandle = <0x186>;
|
|
};
|
|
|
|
rgb0@0 {
|
|
pins = "PB0\0PB1\0PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PB2\0PB3\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PB7\0PB8\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
|
|
function = "lcd0";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x187>;
|
|
};
|
|
|
|
rgb0@1 {
|
|
pins = "PB0\0PB1\0PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PB2\0PB3\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PB7\0PB8\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
|
|
function = "gpio_in";
|
|
phandle = <0x188>;
|
|
};
|
|
|
|
rgb0@2 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
|
|
function = "dpss";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x189>;
|
|
};
|
|
|
|
rgb0@3 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
|
|
function = "gpio_in";
|
|
phandle = <0x18a>;
|
|
};
|
|
|
|
csi_mclk0@0 {
|
|
pins = "PE0";
|
|
function = "mipi0";
|
|
drive-strength = <0x14>;
|
|
phandle = <0xf7>;
|
|
};
|
|
|
|
csi_mclk0@1 {
|
|
pins = "PE0";
|
|
function = "gpio_in";
|
|
phandle = <0xf8>;
|
|
};
|
|
|
|
csi_mclk1@0 {
|
|
pins = "PE5";
|
|
function = "mipi1";
|
|
drive-strength = <0x14>;
|
|
phandle = <0xf9>;
|
|
};
|
|
|
|
csi_mclk1@1 {
|
|
pins = "PE5";
|
|
function = "gpio_in";
|
|
phandle = <0xfa>;
|
|
};
|
|
|
|
csi_mclk2@0 {
|
|
pins = "PE15";
|
|
function = "mipi2";
|
|
drive-strength = <0x14>;
|
|
phandle = <0xfb>;
|
|
};
|
|
|
|
csi_mclk2@1 {
|
|
pins = "PE15";
|
|
function = "gpio_in";
|
|
phandle = <0xfc>;
|
|
};
|
|
|
|
csi_mclk3@0 {
|
|
pins = "PE10";
|
|
function = "mipi3";
|
|
drive-strength = <0x14>;
|
|
phandle = <0xfd>;
|
|
};
|
|
|
|
csi_mclk3@1 {
|
|
pins = "PE10";
|
|
function = "gpio_in";
|
|
phandle = <0xfe>;
|
|
};
|
|
|
|
ncsi_BT656@0 {
|
|
pins = "PK12\0PK14\0PK15\0PK16\0PK17\0PK18\0PK19\0PK20\0PK21\0PK22\0PK23";
|
|
function = "ncsi";
|
|
drive-strength = <0x14>;
|
|
phandle = <0x18b>;
|
|
};
|
|
|
|
ncsi_BT656@1 {
|
|
pins = "PK12\0PK14\0PK15\0PK16\0PK17\0PK18\0PK19\0PK20\0PK21\0PK22\0PK23";
|
|
function = "gpio_in";
|
|
phandle = <0x18c>;
|
|
};
|
|
|
|
ncsi_BT1120@0 {
|
|
pins = "PK12\0PK14\0PK15\0PK16\0PK17\0PK18\0PK19\0PK20\0PK21\0PK22\0PK23\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11\0PE12\0PE15";
|
|
function = "ncsi";
|
|
drive-strength = <0x14>;
|
|
phandle = <0x18d>;
|
|
};
|
|
|
|
ncsi_BT1120@1 {
|
|
pins = "PK12\0PK14\0PK15\0PK16\0PK17\0PK18\0PK19\0PK20\0PK21\0PK22\0PK23\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11\0PE12\0PE15";
|
|
function = "gpio_in";
|
|
phandle = <0x18e>;
|
|
};
|
|
|
|
mipia@0 {
|
|
pins = "PK0\0PK1\0PK2\0PK3\0PK4\0PK5";
|
|
function = "mcsia";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x101>;
|
|
};
|
|
|
|
mipia@1 {
|
|
pins = "PK0\0PK1\0PK2\0PK3\0PK4\0PK5";
|
|
function = "gpio_in";
|
|
phandle = <0x102>;
|
|
};
|
|
|
|
mipib@0 {
|
|
pins = "PK6\0PK7\0PK8\0PK9\0PK10\0PK11";
|
|
function = "mcsib";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x105>;
|
|
};
|
|
|
|
mipib@1 {
|
|
pins = "PK6\0PK7\0PK8\0PK9\0PK10\0PK11";
|
|
function = "gpio_in";
|
|
phandle = <0x106>;
|
|
};
|
|
|
|
mipib_4lane@0 {
|
|
pins = "PK6\0PK7\0PK8\0PK9\0PK10\0PK11";
|
|
function = "mcsib";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x103>;
|
|
};
|
|
|
|
mipib_4lane@1 {
|
|
pins = "PK6\0PK7\0PK8\0PK9\0PK10\0PK11";
|
|
function = "gpio_in";
|
|
phandle = <0x104>;
|
|
};
|
|
|
|
mipic@0 {
|
|
pins = "PK12\0PK13\0PK14\0PK15\0PK16\0PK17";
|
|
function = "mcsic";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x107>;
|
|
};
|
|
|
|
mipic@1 {
|
|
pins = "PK12\0PK13\0PK14\0PK15\0PK16\0PK17";
|
|
function = "gpio_in";
|
|
phandle = <0x108>;
|
|
};
|
|
|
|
mipid@0 {
|
|
pins = "PK18\0PK19\0PK20\0PK21\0PK22\0PK23";
|
|
function = "mcsid";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x10b>;
|
|
};
|
|
|
|
mipid@1 {
|
|
pins = "PK18\0PK19\0PK20\0PK21\0PK22\0PK23";
|
|
function = "gpio_in";
|
|
phandle = <0x10c>;
|
|
};
|
|
|
|
mipid_4lane@0 {
|
|
pins = "PK18\0PK19\0PK20\0PK21\0PK22\0PK23";
|
|
function = "mcsid";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x109>;
|
|
};
|
|
|
|
mipid_4lane@1 {
|
|
pins = "PK18\0PK19\0PK20\0PK21\0PK22\0PK23";
|
|
function = "gpio_in";
|
|
phandle = <0x10a>;
|
|
};
|
|
|
|
test_pins@0 {
|
|
pins = "PB2\0PB5";
|
|
function = "test";
|
|
drive-strength = <0x0a>;
|
|
bias-pull-up;
|
|
phandle = <0x60>;
|
|
};
|
|
|
|
test_pins@1 {
|
|
pins = "PB2\0PB5";
|
|
function = "gpio_in";
|
|
phandle = <0x61>;
|
|
};
|
|
|
|
uart0_pins@0 {
|
|
pins = [00 00];
|
|
function = "uart0";
|
|
phandle = <0x63>;
|
|
};
|
|
|
|
uart0_pins@1 {
|
|
pins = [00 00];
|
|
function = "gpio_in";
|
|
phandle = <0x64>;
|
|
};
|
|
|
|
uart2_pins@0 {
|
|
pins = "PB0\0PB1";
|
|
function = "uart2";
|
|
phandle = <0x68>;
|
|
};
|
|
|
|
uart2_pins@1 {
|
|
pins = "PB0\0PB1";
|
|
function = "gpio_in";
|
|
phandle = <0x69>;
|
|
};
|
|
|
|
uart3_pins@0 {
|
|
pins = "PI11\0PI12";
|
|
function = "uart3";
|
|
phandle = <0x6a>;
|
|
};
|
|
|
|
uart3_pins@1 {
|
|
pins = "PI11\0PI12";
|
|
function = "gpio_in";
|
|
phandle = <0x6b>;
|
|
};
|
|
|
|
uart4_pins@0 {
|
|
pins = "PI0\0PI1";
|
|
function = "uart4";
|
|
phandle = <0x6c>;
|
|
};
|
|
|
|
uart4_pins@1 {
|
|
pins = "PI0\0PI1";
|
|
function = "gpio_in";
|
|
phandle = <0x6d>;
|
|
};
|
|
|
|
uart5_pins@0 {
|
|
pins = "PI2\0PI3";
|
|
function = "uart5";
|
|
phandle = <0x6e>;
|
|
};
|
|
|
|
uart5_pins@1 {
|
|
pins = "PI2\0PI3";
|
|
function = "gpio_in";
|
|
phandle = <0x6f>;
|
|
};
|
|
|
|
uart6_pins@0 {
|
|
pins = "PI6\0PI7";
|
|
function = "uart6";
|
|
phandle = <0x70>;
|
|
};
|
|
|
|
uart6_pins@1 {
|
|
pins = "PI6\0PI7";
|
|
function = "gpio_in";
|
|
phandle = <0x71>;
|
|
};
|
|
|
|
uart7_pins@0 {
|
|
pins = "PB13\0PB14";
|
|
function = "uart7";
|
|
phandle = <0x72>;
|
|
};
|
|
|
|
uart7_pins@1 {
|
|
pins = "PB13\0PB14";
|
|
function = "gpio_in";
|
|
phandle = <0x73>;
|
|
};
|
|
|
|
pwm0_0@0 {
|
|
pins = "PD23";
|
|
function = "pwm0_0";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x8a>;
|
|
};
|
|
|
|
pwm0_0@1 {
|
|
pins = "PD23";
|
|
function = "gpio_in";
|
|
phandle = <0x8b>;
|
|
};
|
|
|
|
pwm0_1@0 {
|
|
pins = "PI0";
|
|
function = "pwm0_1";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x8c>;
|
|
};
|
|
|
|
pwm0_1@1 {
|
|
pins = "PI0";
|
|
function = "gpio_in";
|
|
phandle = <0x8d>;
|
|
};
|
|
|
|
pwm0_2@0 {
|
|
pins = "PB11";
|
|
function = "pwm0_2";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x8e>;
|
|
};
|
|
|
|
pwm0_2@1 {
|
|
pins = "PB11";
|
|
function = "gpio_in";
|
|
phandle = <0x8f>;
|
|
};
|
|
|
|
pwm0_3@0 {
|
|
pins = "PE10";
|
|
function = "pwm0_3";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x90>;
|
|
};
|
|
|
|
pwm0_3@1 {
|
|
pins = "PE10";
|
|
function = "gpio_in";
|
|
phandle = <0x91>;
|
|
};
|
|
|
|
pwm0_4@0 {
|
|
pins = "PB13";
|
|
function = "pwm0_4";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x92>;
|
|
};
|
|
|
|
pwm0_4@1 {
|
|
pins = "PB13";
|
|
function = "gpio_in";
|
|
phandle = <0x93>;
|
|
};
|
|
|
|
pwm0_5@0 {
|
|
pins = "PB14";
|
|
function = "pwm0_5";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x94>;
|
|
};
|
|
|
|
pwm0_5@1 {
|
|
pins = "PB14";
|
|
function = "gpio_in";
|
|
phandle = <0x95>;
|
|
};
|
|
|
|
pwm0_6@0 {
|
|
pins = "PB0";
|
|
function = "pwm0_6";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x96>;
|
|
};
|
|
|
|
pwm0_6@1 {
|
|
pins = "PB0";
|
|
function = "gpio_in";
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
pwm0_7@0 {
|
|
pins = "PB1";
|
|
function = "pwm0_7";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x98>;
|
|
};
|
|
|
|
pwm0_7@1 {
|
|
pins = "PB1";
|
|
function = "gpio_in";
|
|
phandle = <0x99>;
|
|
};
|
|
|
|
pwm0_8@0 {
|
|
pins = "PB4";
|
|
function = "pwm0_8";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x9a>;
|
|
};
|
|
|
|
pwm0_8@1 {
|
|
pins = "PB4";
|
|
function = "gpio_in";
|
|
phandle = <0x9b>;
|
|
};
|
|
|
|
pwm0_9@0 {
|
|
pins = "PB5";
|
|
function = "pwm0_9";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x9c>;
|
|
};
|
|
|
|
pwm0_9@1 {
|
|
pins = "PB5";
|
|
function = "gpio_in";
|
|
phandle = <0x9d>;
|
|
};
|
|
|
|
pwm0_10@0 {
|
|
pins = "PB6";
|
|
function = "pwm0_10";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0x9e>;
|
|
};
|
|
|
|
pwm0_10@1 {
|
|
pins = "PB6";
|
|
function = "gpio_in";
|
|
phandle = <0x9f>;
|
|
};
|
|
|
|
pwm0_11@0 {
|
|
pins = "PB7";
|
|
function = "pwm0_11";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0xa0>;
|
|
};
|
|
|
|
pwm0_11@1 {
|
|
pins = "PB7";
|
|
function = "gpio_in";
|
|
phandle = <0xa1>;
|
|
};
|
|
|
|
pwm0_12@0 {
|
|
pins = "PI11";
|
|
function = "pwm0_12";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
pwm0_12@1 {
|
|
pins = "PI11";
|
|
function = "gpio_in";
|
|
phandle = <0xa3>;
|
|
};
|
|
|
|
pwm0_13@0 {
|
|
pins = "PI12";
|
|
function = "pwm0_13";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0xa4>;
|
|
};
|
|
|
|
pwm0_13@1 {
|
|
pins = "PI12";
|
|
function = "gpio_in";
|
|
phandle = <0xa5>;
|
|
};
|
|
|
|
pwm0_14@0 {
|
|
pins = "PI13";
|
|
function = "pwm0_14";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0xa6>;
|
|
};
|
|
|
|
pwm0_14@1 {
|
|
pins = "PI13";
|
|
function = "gpio_in";
|
|
phandle = <0xa7>;
|
|
};
|
|
|
|
pwm0_15@0 {
|
|
pins = "PI14";
|
|
function = "pwm0_15";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0xa8>;
|
|
};
|
|
|
|
pwm0_15@1 {
|
|
pins = "PI14";
|
|
function = "gpio_in";
|
|
phandle = <0xa9>;
|
|
};
|
|
|
|
ledc@0 {
|
|
pins = "PE5";
|
|
function = "ledc";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0xb9>;
|
|
};
|
|
|
|
ledc@1 {
|
|
pins = "PE5";
|
|
function = "gpio_in";
|
|
phandle = <0xba>;
|
|
};
|
|
|
|
irrx@0 {
|
|
pins = "PH19";
|
|
function = "cir";
|
|
phandle = <0xbb>;
|
|
};
|
|
|
|
irrx@1 {
|
|
pins = "PH19";
|
|
function = "gpio_in";
|
|
phandle = <0xbc>;
|
|
};
|
|
|
|
irtx@0 {
|
|
pins = "PH18";
|
|
function = "cir";
|
|
phandle = <0xbf>;
|
|
};
|
|
|
|
irtx@1 {
|
|
pins = "PH18";
|
|
function = "gpio_in";
|
|
phandle = <0xc0>;
|
|
};
|
|
|
|
twi0@0 {
|
|
pins = "PH0\0PH1";
|
|
function = "twi0";
|
|
drive-strength = <0x28>;
|
|
bias-pull-up;
|
|
phandle = <0xc1>;
|
|
};
|
|
|
|
twi0@1 {
|
|
pins = "PH0\0PH1";
|
|
function = "gpio_in";
|
|
phandle = <0xc2>;
|
|
};
|
|
|
|
twi1@0 {
|
|
pins = "PB4\0PB5";
|
|
function = "twi1";
|
|
drive-strength = <0x0a>;
|
|
bias-pull-up;
|
|
phandle = <0xc3>;
|
|
};
|
|
|
|
twi1@1 {
|
|
pins = "PB4\0PB5";
|
|
function = "gpio_in";
|
|
phandle = <0xc4>;
|
|
};
|
|
|
|
twi3@0 {
|
|
pins = "PE3\0PE4";
|
|
function = "twi3";
|
|
drive-strength = <0x28>;
|
|
bias-pull-up;
|
|
phandle = <0xc5>;
|
|
};
|
|
|
|
twi3@1 {
|
|
pins = "PE3\0PE4";
|
|
function = "twi3";
|
|
drive-strength = <0x28>;
|
|
bias-pull-up;
|
|
phandle = <0xc6>;
|
|
};
|
|
|
|
twi4@0 {
|
|
pins = "PI0\0PI1";
|
|
function = "twi4";
|
|
drive-strength = <0x14>;
|
|
bias-pull-up;
|
|
phandle = <0xc7>;
|
|
};
|
|
|
|
twi4@1 {
|
|
pins = "PI0\0PI1";
|
|
function = "gpio_in";
|
|
phandle = <0xc8>;
|
|
};
|
|
|
|
twi5@0 {
|
|
pins = "PI8\0PI9";
|
|
function = "twi5";
|
|
drive-strength = <0x0a>;
|
|
bias-pull-up;
|
|
phandle = <0xc9>;
|
|
};
|
|
|
|
twi5@1 {
|
|
pins = "PI8\0PI9";
|
|
function = "gpio_in";
|
|
phandle = <0xca>;
|
|
};
|
|
|
|
rgb24@0 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21\0PD22\0PD23\0PD24\0PD25\0PD26\0PD27";
|
|
function = "dpss";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0x5c>;
|
|
};
|
|
|
|
rgb24@1 {
|
|
pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21\0PD22\0PD23\0PD24\0PD25\0PD26\0PD27";
|
|
function = "gpio_in";
|
|
phandle = <0x5d>;
|
|
};
|
|
|
|
ncsi@0 {
|
|
pins = "PK12\0PK14\0PK15\0PK16\0PK17\0PK18\0PK19\0PK20\0PK21\0PK22\0PK23\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11\0PE12\0PE15";
|
|
function = "ncsi";
|
|
drive-strength = <0x14>;
|
|
phandle = <0xff>;
|
|
};
|
|
|
|
ncsi@1 {
|
|
pins = "PK12\0PK14\0PK15\0PK16\0PK17\0PK18\0PK19\0PK20\0PK21\0PK22\0PK23\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11\0PE12\0PE15";
|
|
function = "gpio_in";
|
|
phandle = <0x100>;
|
|
};
|
|
|
|
i2s1@0 {
|
|
pins = "PG10\0PG11\0PG12";
|
|
function = "i2s1";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x117>;
|
|
};
|
|
|
|
i2s1@1 {
|
|
pins = "PG10\0PG11\0PG12\0PG13\0PG14";
|
|
function = "io_disabled";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x11a>;
|
|
};
|
|
|
|
i2s1@2 {
|
|
pins = "PG13";
|
|
function = "i2s1_dout";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x118>;
|
|
};
|
|
|
|
i2s1@3 {
|
|
pins = "PG14";
|
|
function = "i2s1_din";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x119>;
|
|
};
|
|
|
|
owa@0 {
|
|
pins = "PH7";
|
|
function = "owa";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x112>;
|
|
};
|
|
|
|
owa@1 {
|
|
pins = "PH7";
|
|
function = "io_disabled";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x113>;
|
|
};
|
|
|
|
nand0@0 {
|
|
pins = "PC0\0PC1\0PC2\0PC5\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14\0PC15\0PC16";
|
|
function = "nand0";
|
|
drive-strength = <0x1e>;
|
|
phandle = <0xe7>;
|
|
};
|
|
|
|
nand0@1 {
|
|
pins = "PC4\0PC6\0PC3\0PC7";
|
|
function = "nand0";
|
|
drive-strength = <0x1e>;
|
|
bias-pull-up;
|
|
phandle = <0xe8>;
|
|
};
|
|
|
|
nand0@2 {
|
|
pins = "PC0\0PC1\0PC2\0PC3\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14\0PC15\0PC16";
|
|
function = "io_disabled";
|
|
drive-strength = <0x0a>;
|
|
phandle = <0xe9>;
|
|
};
|
|
|
|
i2s0@0 {
|
|
pins = "PB4\0PB5\0PB6";
|
|
function = "i2s0";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x18f>;
|
|
};
|
|
|
|
i2s0@1 {
|
|
pins = "PB4\0PB5\0PB6\0PB7\0PB8";
|
|
function = "io_disabled";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x190>;
|
|
};
|
|
|
|
i2s0@2 {
|
|
pins = "PB7";
|
|
function = "i2s0_dout";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x191>;
|
|
};
|
|
|
|
i2s0@3 {
|
|
pins = "PB8";
|
|
function = "i2s0_din";
|
|
drive-strength = <0x14>;
|
|
bias-disable;
|
|
phandle = <0x192>;
|
|
};
|
|
|
|
gmac1@0 {
|
|
pins = "PJ0\0PJ1\0PJ2\0PJ3\0PJ4\0PJ5\0PJ6\0PJ7\0PJ8\0PJ9\0PJ10\0PJ11\0PJ12\0PJ13\0PJ14\0PJ15";
|
|
drive-strength = <0x28>;
|
|
function = "gmac1";
|
|
bias-pull-up;
|
|
phandle = <0x127>;
|
|
};
|
|
|
|
gmac1@1 {
|
|
pins = "PJ0\0PJ1\0PJ2\0PJ3\0PJ4\0PJ5\0PJ6\0PJ7\0PJ8\0PJ9\0PJ10\0PJ11\0PJ12\0PJ13\0PJ14\0PJ15";
|
|
function = "gpio_in";
|
|
phandle = <0x128>;
|
|
};
|
|
|
|
spi1_pin_default {
|
|
pins = "PI2\0PI3\0PI4\0PI5";
|
|
function = "spi1";
|
|
phandle = <0xe3>;
|
|
};
|
|
|
|
spi1_pin_sleep {
|
|
pins = "PI2\0PI3\0PI4\0PI5";
|
|
function = "gpio_in";
|
|
phandle = <0xe4>;
|
|
};
|
|
|
|
spi2_pin_default {
|
|
pins = "PB0\0PB1\0PB2\0PB3";
|
|
function = "spi2";
|
|
phandle = <0xe5>;
|
|
};
|
|
|
|
spi2_pin_sleep {
|
|
pins = "PB0\0PB1\0PB2\0PB3";
|
|
function = "gpio_in";
|
|
phandle = <0xe6>;
|
|
};
|
|
};
|
|
|
|
pinctrl_test@2000000 {
|
|
reg = <0x00 0x00 0x00 0x00>;
|
|
compatible = "allwinner,sunxi-pinctrl-test";
|
|
device_type = "pinctrl-test";
|
|
pinctrl-0 = <0x60>;
|
|
pinctrl-1 = <0x61>;
|
|
pinctrl-names = "default\0sleep";
|
|
test-gpios = <0x4b 0x01 0x04 0x01>;
|
|
suspend-gpios = <0x62 0x00 0x04 0x01>;
|
|
wakeup-source;
|
|
interrupt-parent = <0x4b>;
|
|
interrupts = <0x01 0x06 0x04>;
|
|
phandle = <0x193>;
|
|
};
|
|
|
|
ths0@200a000 {
|
|
compatible = "allwinner,sun55iw3p1-ths0";
|
|
reg = <0x00 0x200a000 0x00 0x400>;
|
|
clocks = <0x1a 0x87 0x1a 0x83>;
|
|
clock-names = "bus\0sclk";
|
|
resets = <0x1a 0x2f>;
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x17>;
|
|
};
|
|
|
|
ths0@2009400 {
|
|
compatible = "allwinner,sun55iw3p1-ths1";
|
|
reg = <0x00 0x2009400 0x00 0x400>;
|
|
clocks = <0x1a 0x87 0x1a 0x84>;
|
|
clock-names = "bus\0sclk";
|
|
resets = <0x1a 0x2f>;
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x12>;
|
|
};
|
|
|
|
timer@3008000 {
|
|
compatible = "allwinner,sun50i-timer";
|
|
device_type = "soc_timer";
|
|
reg = <0x00 0x3008000 0x00 0x400>;
|
|
interrupt-parent = <0x18>;
|
|
interrupts = <0x00 0x37 0x04>;
|
|
clock-names = "parent\0bus\0timer0-mod\0timer1-mod";
|
|
clocks = <0x22 0x1a 0x45 0x1a 0x4b 0x1a 0x4c>;
|
|
resets = <0x1a 0x0d>;
|
|
phandle = <0x194>;
|
|
};
|
|
|
|
arm_pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupt-parent = <0x18>;
|
|
interrupts = <0x01 0x07 0x04>;
|
|
};
|
|
|
|
dump_reg@40000 {
|
|
compatible = "allwinner,sunxi-dump-reg";
|
|
reg = <0x00 0x40000 0x00 0x04>;
|
|
phandle = <0x195>;
|
|
};
|
|
|
|
soft_jtag_master@0 {
|
|
compatible = "allwinner,soft-jtag-master";
|
|
tdi-gpios = <0x62 0x00 0x02 0x00>;
|
|
tdo-gpios = <0x62 0x00 0x03 0x00>;
|
|
tck-gpios = <0x4b 0x01 0x0b 0x00>;
|
|
tms-gpios = <0x4b 0x01 0x0c 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x196>;
|
|
};
|
|
|
|
pio-18 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "pio-18";
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
phandle = <0x5e>;
|
|
};
|
|
|
|
pio-28 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "pio-28";
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
phandle = <0x197>;
|
|
};
|
|
|
|
pio-33 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "pio-33";
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
phandle = <0x5f>;
|
|
};
|
|
|
|
uart@2500000 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x2500000 0x00 0x400>;
|
|
interrupts = <0x00 0x02 0x04>;
|
|
clocks = <0x1a 0x6c>;
|
|
resets = <0x1a 0x1e>;
|
|
uart0_port = <0x00>;
|
|
uart0_type = <0x02>;
|
|
status = "okay";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x63>;
|
|
pinctrl-1 = <0x64>;
|
|
uart-supply = <0x65>;
|
|
phandle = <0x198>;
|
|
};
|
|
|
|
uart@2500400 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
device_type = "uart1";
|
|
reg = <0x00 0x2500400 0x00 0x400>;
|
|
interrupts = <0x00 0x03 0x04>;
|
|
sunxi,uart-fifosize = <0x40>;
|
|
clocks = <0x1a 0x6b>;
|
|
clock-names = "uart1";
|
|
resets = <0x1a 0x1d>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x66>;
|
|
pinctrl-1 = <0x67>;
|
|
uart1_port = <0x01>;
|
|
uart1_type = <0x04>;
|
|
status = "okay";
|
|
phandle = <0x199>;
|
|
};
|
|
|
|
uart@2500800 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x2500800 0x00 0x400>;
|
|
interrupts = <0x00 0x04 0x04>;
|
|
clocks = <0x1a 0x6a>;
|
|
resets = <0x1a 0x1c>;
|
|
uart2_port = <0x02>;
|
|
uart2_type = <0x04>;
|
|
sunxi,uart-fifosize = <0x80>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x68>;
|
|
pinctrl-1 = <0x69>;
|
|
phandle = <0x19a>;
|
|
};
|
|
|
|
uart@2500c00 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x2500c00 0x00 0x400>;
|
|
interrupts = <0x00 0x05 0x04>;
|
|
clocks = <0x1a 0x69>;
|
|
resets = <0x1a 0x1b>;
|
|
uart3_port = <0x03>;
|
|
uart3_type = <0x04>;
|
|
sunxi,uart-fifosize = <0x80>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x6a>;
|
|
pinctrl-1 = <0x6b>;
|
|
phandle = <0x19b>;
|
|
};
|
|
|
|
uart@2501000 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x2501000 0x00 0x400>;
|
|
interrupts = <0x00 0x06 0x04>;
|
|
clocks = <0x1a 0x68>;
|
|
resets = <0x1a 0x1a>;
|
|
uart4_port = <0x04>;
|
|
uart4_type = <0x04>;
|
|
sunxi,uart-fifosize = <0x80>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x6c>;
|
|
pinctrl-1 = <0x6d>;
|
|
phandle = <0x19c>;
|
|
};
|
|
|
|
uart@2501400 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x2501400 0x00 0x400>;
|
|
interrupts = <0x00 0x07 0x04>;
|
|
clocks = <0x1a 0x67>;
|
|
resets = <0x1a 0x19>;
|
|
uart5_port = <0x05>;
|
|
uart5_type = <0x04>;
|
|
sunxi,uart-fifosize = <0x80>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x6e>;
|
|
pinctrl-1 = <0x6f>;
|
|
phandle = <0x19d>;
|
|
};
|
|
|
|
uart@2501800 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x2501800 0x00 0x400>;
|
|
interrupts = <0x00 0x08 0x04>;
|
|
clocks = <0x1a 0x66>;
|
|
resets = <0x1a 0x18>;
|
|
uart6_port = <0x06>;
|
|
uart6_type = <0x04>;
|
|
sunxi,uart-fifosize = <0x80>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x70>;
|
|
pinctrl-1 = <0x71>;
|
|
phandle = <0x19e>;
|
|
};
|
|
|
|
uart@2501c00 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x2501c00 0x00 0x400>;
|
|
interrupts = <0x00 0x09 0x04>;
|
|
clocks = <0x1a 0x65>;
|
|
resets = <0x1a 0x17>;
|
|
uart7_port = <0x07>;
|
|
uart7_type = <0x04>;
|
|
sunxi,uart-fifosize = <0x80>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x72>;
|
|
pinctrl-1 = <0x73>;
|
|
phandle = <0x19f>;
|
|
};
|
|
|
|
uart@7080000 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x7080000 0x00 0x400>;
|
|
interrupts = <0x00 0xa2 0x04>;
|
|
clocks = <0x19 0x10>;
|
|
resets = <0x19 0x07>;
|
|
uart8_port = <0x08>;
|
|
uart8_type = <0x02>;
|
|
sunxi,uart-fifosize = <0x40>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x74>;
|
|
pinctrl-1 = <0x75>;
|
|
phandle = <0x1a0>;
|
|
};
|
|
|
|
uart@7080400 {
|
|
compatible = "allwinner,sun55i-uart";
|
|
reg = <0x00 0x7080400 0x00 0x400>;
|
|
interrupts = <0x00 0xa3 0x04>;
|
|
clocks = <0x19 0x0f>;
|
|
resets = <0x19 0x06>;
|
|
uart9_port = <0x09>;
|
|
uart9_type = <0x02>;
|
|
sunxi,uart-fifosize = <0x40>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x76>;
|
|
pinctrl-1 = <0x77>;
|
|
phandle = <0x1a1>;
|
|
};
|
|
|
|
dma-controller@3002000 {
|
|
compatible = "allwinner,dma-v105";
|
|
reg = <0x00 0x3002000 0x00 0x1000>;
|
|
interrupts = <0x00 0x32 0x04>;
|
|
clocks = <0x1a 0x42 0x1a 0x59>;
|
|
clock-names = "bus\0mbus";
|
|
dma-channels = <0x08>;
|
|
dma-requests = <0x36>;
|
|
resets = <0x1a 0x09>;
|
|
#dma-cells = <0x01>;
|
|
status = "okay";
|
|
phandle = <0xb8>;
|
|
};
|
|
|
|
dma1-controller@7121000 {
|
|
compatible = "allwinner,dma-v104";
|
|
reg = <0x00 0x7121000 0x00 0x1000>;
|
|
interrupts = <0x00 0xc5 0x04>;
|
|
clocks = <0x78 0x22 0x78 0x27 0x78 0x26>;
|
|
clock-names = "bus\0mbus\0mcu-mbus";
|
|
dma-channels = <0x08>;
|
|
dma-requests = <0x0f>;
|
|
resets = <0x78 0x0d>;
|
|
#dma-cells = <0x01>;
|
|
status = "okay";
|
|
phandle = <0xcb>;
|
|
};
|
|
|
|
npu@7122000 {
|
|
compatible = "allwinner,npu";
|
|
reg = <0x00 0x7122000 0x00 0x1000>;
|
|
device_type = "npu";
|
|
dev_name = "npu";
|
|
interrupts = <0x00 0xc7 0x04>;
|
|
clocks = <0x1a 0x41 0x1a 0x2b 0x78 0x18 0x78 0x19>;
|
|
clock-names = "clk_npu\0clk_parent\0npu-aclk\0npu-hclk";
|
|
operating-points-v2 = <0x79>;
|
|
resets = <0x78 0x09>;
|
|
reset-names = "npu_rst";
|
|
interrupt-names = "npu";
|
|
npu-vf = <0x2b8>;
|
|
npu-regulator = <0x01>;
|
|
power-domains = <0x21 0x01>;
|
|
status = "okay";
|
|
phandle = <0x1a2>;
|
|
};
|
|
|
|
npu-opp-table {
|
|
compatible = "allwinner,sun55i-operating-points";
|
|
opp-shared;
|
|
phandle = <0x79>;
|
|
|
|
opp-546 {
|
|
opp-hz = <0x208b4c80>;
|
|
opp-microvolt-vf1 = <0xe09c0>;
|
|
opp-microvolt-vf12 = <0xe09c0>;
|
|
opp-microvolt-vf2 = <0xe09c0>;
|
|
opp-microvolt-vf21 = <0xe09c0>;
|
|
opp-microvolt-vf3 = <0xe09c0>;
|
|
opp-microvolt-vf31 = <0xe09c0>;
|
|
opp-microvolt-vf32 = <0xe09c0>;
|
|
opp-microvolt-vf4 = <0xe09c0>;
|
|
opp-microvolt-vf5 = <0xe09c0>;
|
|
opp-microvolt-vf52 = <0xe09c0>;
|
|
phandle = <0x1a3>;
|
|
};
|
|
|
|
opp-696 {
|
|
opp-hz = <0x297c1e00>;
|
|
opp-microvolt-vf1 = <0x100590>;
|
|
opp-microvolt-vf12 = <0x100590>;
|
|
opp-microvolt-vf2 = <0x100590>;
|
|
opp-microvolt-vf21 = <0x100590>;
|
|
opp-microvolt-vf3 = <0xf4240>;
|
|
opp-microvolt-vf31 = <0xf4240>;
|
|
opp-microvolt-vf32 = <0xf4240>;
|
|
opp-microvolt-vf4 = <0xf4240>;
|
|
opp-microvolt-vf5 = <0x100590>;
|
|
opp-microvolt-vf52 = <0x100590>;
|
|
phandle = <0x1a4>;
|
|
};
|
|
};
|
|
|
|
watchdog@2050000 {
|
|
compatible = "allwinner,wdt-v103";
|
|
reg = <0x00 0x2050000 0x00 0x20>;
|
|
interrupts = <0x00 0x3f 0x04>;
|
|
phandle = <0x1a5>;
|
|
};
|
|
|
|
gpadc0@2009000 {
|
|
compatible = "allwinner,sunxi-gpadc";
|
|
reg = <0x00 0x2009000 0x00 0x400>;
|
|
interrupts = <0x00 0x3d 0x04>;
|
|
clocks = <0x1a 0x85>;
|
|
clock-names = "bus";
|
|
resets = <0x1a 0x2e>;
|
|
status = "disabled";
|
|
channel_num = <0x02>;
|
|
channel_select = <0x03>;
|
|
channel_data_select = <0x03>;
|
|
channel_compare_select = <0x03>;
|
|
channel_cld_select = <0x03>;
|
|
channel_chd_select = <0x03>;
|
|
channel0_compare_lowdata = <0x19f0a0>;
|
|
channel0_compare_higdata = <0x124f80>;
|
|
channel1_compare_lowdata = <0x704e0>;
|
|
channel1_compare_higdata = <0x124f80>;
|
|
phandle = <0x1a6>;
|
|
};
|
|
|
|
gpadc1@2009c00 {
|
|
compatible = "allwinner,sunxi-gpadc";
|
|
reg = <0x00 0x2009c00 0x00 0x400>;
|
|
interrupts = <0x00 0x40 0x04>;
|
|
clocks = <0x1a 0x86>;
|
|
clock-names = "bus";
|
|
resets = <0x1a 0x2d>;
|
|
status = "disabled";
|
|
channel_num = <0x02>;
|
|
channel_select = <0x03>;
|
|
channel_data_select = <0x03>;
|
|
channel_compare_select = <0x03>;
|
|
channel_cld_select = <0x03>;
|
|
channel_chd_select = <0x03>;
|
|
channel0_compare_lowdata = <0x19f0a0>;
|
|
channel0_compare_higdata = <0x124f80>;
|
|
channel1_compare_lowdata = <0x704e0>;
|
|
channel1_compare_higdata = <0x124f80>;
|
|
phandle = <0x1a7>;
|
|
};
|
|
|
|
dsp0_rproc@0 {
|
|
compatible = "allwinner,hifi4-rproc";
|
|
clock-frequency = <0x23c34600>;
|
|
clocks = <0x1a 0x02 0x78 0x04 0x1a 0xb5 0x78 0x17 0x19 0x00>;
|
|
clock-names = "pll\0mcu-mod\0mod\0cfg\0ahbs";
|
|
resets = <0x78 0x0b 0x78 0x08 0x78 0x0c>;
|
|
reset-names = "mod-rst\0cfg-rst\0dbg-rst";
|
|
reg = <0x00 0x7010364 0x00 0x04 0x00 0x7100000 0x00 0x40>;
|
|
reg-names = "sram-for-cpux\0hifi4-cfg";
|
|
firmware-name = "amp_dsp0.bin";
|
|
power-domains = <0x21 0x00 0x21 0x03>;
|
|
power-domain-names = "pd_dsp\0pd_sram";
|
|
status = "disabled";
|
|
phandle = <0x1a8>;
|
|
};
|
|
|
|
e906_rproc@7130000 {
|
|
compatible = "allwinner,e906-rproc";
|
|
clocks = <0x78 0x25 0x78 0x28 0x78 0x29>;
|
|
clock-names = "pubsram\0mod\0cfg";
|
|
resets = <0x78 0x0e 0x78 0x0f 0x78 0x11 0x78 0x10>;
|
|
reset-names = "pubsram-rst\0mod-rst\0cfg-rst\0dbg-rst";
|
|
firmware-name = "amp_rv0.bin";
|
|
reg = <0x00 0x7130000 0x00 0x1000>;
|
|
reg-names = "e906-cfg";
|
|
power-domains = <0x21 0x04 0x21 0x03>;
|
|
power-domain-names = "pd_riscv\0pd_sram";
|
|
status = "disabled";
|
|
phandle = <0x1a9>;
|
|
};
|
|
|
|
msgbox@3003000 {
|
|
compatible = "allwinner,sun55iw3-msgbox";
|
|
#mbox-cells = <0x01>;
|
|
reg = <0x00 0x3003000 0x00 0x1000 0x00 0x7120000 0x00 0x1000 0x00 0x7094000 0x00 0x1000 0x00 0x7136000 0x00 0x1000>;
|
|
interrupts = <0x00 0x00 0x04 0x00 0x01 0x04 0x00 0xb5 0x04 0x00 0xae 0x04>;
|
|
clocks = <0x1a 0x43>;
|
|
clock-names = "msgbox";
|
|
resets = <0x1a 0x0b>;
|
|
reset-names = "rst";
|
|
local_id = <0x00>;
|
|
phandle = <0x1aa>;
|
|
};
|
|
|
|
hwspinlock@3005000 {
|
|
compatible = "allwinner,sunxi-hwspinlock";
|
|
reg = <0x00 0x3005000 0x00 0x1000>;
|
|
#hwlock-cells = <0x01>;
|
|
clocks = <0x1a 0x44>;
|
|
clock-names = "clk_hwspinlock_bus";
|
|
resets = <0x1a 0x0c>;
|
|
reset-names = "rst";
|
|
num-locks = <0x20>;
|
|
status = "okay";
|
|
phandle = <0x1ab>;
|
|
};
|
|
|
|
pwm0@2000c00 {
|
|
#pwm-cells = <0x03>;
|
|
compatible = "allwinner,sunxi-pwm-v201";
|
|
reg = <0x00 0x2000c00 0x00 0x400>;
|
|
clocks = <0x1a 0x48>;
|
|
interrupts = <0x00 0x13 0x04>;
|
|
resets = <0x1a 0x10>;
|
|
pwm-number = <0x10>;
|
|
pwm-base = <0x00>;
|
|
sunxi-pwms = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89>;
|
|
status = "okay";
|
|
phandle = <0x12b>;
|
|
};
|
|
|
|
pwm0_0@2000c10 {
|
|
compatible = "allwinner,sunxi-pwm0";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c10 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "okay";
|
|
pinctrl-0 = <0x8a>;
|
|
pinctrl-1 = <0x8b>;
|
|
phandle = <0x7a>;
|
|
};
|
|
|
|
pwm0_1@2000c11 {
|
|
compatible = "allwinner,sunxi-pwm1";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c11 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x8c>;
|
|
pinctrl-1 = <0x8d>;
|
|
phandle = <0x7b>;
|
|
};
|
|
|
|
pwm0_2@2000c12 {
|
|
compatible = "allwinner,sunxi-pwm2";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c12 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x8e>;
|
|
pinctrl-1 = <0x8f>;
|
|
phandle = <0x7c>;
|
|
};
|
|
|
|
pwm0_3@2000c13 {
|
|
compatible = "allwinner,sunxi-pwm3";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c13 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "okay";
|
|
pinctrl-0 = <0x90>;
|
|
pinctrl-1 = <0x91>;
|
|
phandle = <0x7d>;
|
|
};
|
|
|
|
pwm0_4@2000c14 {
|
|
compatible = "allwinner,sunxi-pwm4";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c14 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x92>;
|
|
pinctrl-1 = <0x93>;
|
|
phandle = <0x7e>;
|
|
};
|
|
|
|
pwm0_5@2000c15 {
|
|
compatible = "allwinner,sunxi-pwm5";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c15 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x94>;
|
|
pinctrl-1 = <0x95>;
|
|
phandle = <0x7f>;
|
|
};
|
|
|
|
pwm0_6@2000c16 {
|
|
compatible = "allwinner,sunxi-pwm6";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c16 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x96>;
|
|
pinctrl-1 = <0x97>;
|
|
phandle = <0x80>;
|
|
};
|
|
|
|
pwm0_7@2000c17 {
|
|
compatible = "allwinner,sunxi-pwm7";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c17 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x98>;
|
|
pinctrl-1 = <0x99>;
|
|
phandle = <0x81>;
|
|
};
|
|
|
|
pwm0_8@2000c18 {
|
|
compatible = "allwinner,sunxi-pwm8";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c18 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x9a>;
|
|
pinctrl-1 = <0x9b>;
|
|
phandle = <0x82>;
|
|
};
|
|
|
|
pwm0_9@2000c19 {
|
|
compatible = "allwinner,sunxi-pwm9";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c19 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x9c>;
|
|
pinctrl-1 = <0x9d>;
|
|
phandle = <0x83>;
|
|
};
|
|
|
|
pwm0_10@2000c1a {
|
|
compatible = "allwinner,sunxi-pwm10";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c1a 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0x9e>;
|
|
pinctrl-1 = <0x9f>;
|
|
phandle = <0x84>;
|
|
};
|
|
|
|
pwm0_11@2000c1b {
|
|
compatible = "allwinner,sunxi-pwm11";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c1b 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0xa0>;
|
|
pinctrl-1 = <0xa1>;
|
|
phandle = <0x85>;
|
|
};
|
|
|
|
pwm0_12@2000c1c {
|
|
compatible = "allwinner,sunxi-pwm12";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c1c 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0xa2>;
|
|
pinctrl-1 = <0xa3>;
|
|
phandle = <0x86>;
|
|
};
|
|
|
|
pwm0_13@2000c1d {
|
|
compatible = "allwinner,sunxi-pwm13";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c1d 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0xa4>;
|
|
pinctrl-1 = <0xa5>;
|
|
phandle = <0x87>;
|
|
};
|
|
|
|
pwm0_14@2000c1e {
|
|
compatible = "allwinner,sunxi-pwm14";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c1e 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0xa6>;
|
|
pinctrl-1 = <0xa7>;
|
|
phandle = <0x88>;
|
|
};
|
|
|
|
pwm0_15@2000c1f {
|
|
compatible = "allwinner,sunxi-pwm15";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2000c1f 0x00 0x04>;
|
|
reg_base = <0x2000c00>;
|
|
status = "disabled";
|
|
pinctrl-0 = <0xa8>;
|
|
pinctrl-1 = <0xa9>;
|
|
phandle = <0x89>;
|
|
};
|
|
|
|
pwm1@2051000 {
|
|
#pwm-cells = <0x03>;
|
|
compatible = "allwinner,sunxi-pwm-v201";
|
|
reg = <0x00 0x2051000 0x00 0x400>;
|
|
clocks = <0x1a 0x47>;
|
|
interrupts = <0x00 0x8e 0x04>;
|
|
resets = <0x1a 0x0f>;
|
|
pwm-number = <0x04>;
|
|
pwm-base = <0x10>;
|
|
sunxi-pwms = <0xaa 0xab 0xac 0xad>;
|
|
status = "disabled";
|
|
phandle = <0x1ac>;
|
|
};
|
|
|
|
pwm1_0@2051010 {
|
|
compatible = "allwinner,sunxi-pwm16";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2051010 0x00 0x04>;
|
|
reg_base = <0x2051000>;
|
|
status = "disabled";
|
|
phandle = <0xaa>;
|
|
};
|
|
|
|
pwm1_1@2051011 {
|
|
compatible = "allwinner,sunxi-pwm17";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2051011 0x00 0x04>;
|
|
reg_base = <0x2051000>;
|
|
status = "disabled";
|
|
phandle = <0xab>;
|
|
};
|
|
|
|
pwm1_2@2051012 {
|
|
compatible = "allwinner,sunxi-pwm18";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2051012 0x00 0x04>;
|
|
reg_base = <0x2051000>;
|
|
status = "disabled";
|
|
phandle = <0xac>;
|
|
};
|
|
|
|
pwm1_3@2051013 {
|
|
compatible = "allwinner,sunxi-pwm19";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x2051013 0x00 0x04>;
|
|
reg_base = <0x2051000>;
|
|
status = "disabled";
|
|
phandle = <0xad>;
|
|
};
|
|
|
|
s_pwm0@7020c00 {
|
|
#pwm-cells = <0x03>;
|
|
compatible = "allwinner,sunxi-pwm-v202";
|
|
reg = <0x00 0x7020c00 0x00 0x400>;
|
|
clocks = <0x19 0x08 0x19 0x09>;
|
|
interrupts = <0x00 0xa8 0x04>;
|
|
clock-names = "clk_pwm\0clk_bus_pwm";
|
|
resets = <0x19 0x01>;
|
|
pwm-number = <0x02>;
|
|
pwm-base = <0x14>;
|
|
sunxi-pwms = <0xae 0xaf>;
|
|
status = "disabled";
|
|
phandle = <0x1ad>;
|
|
};
|
|
|
|
s_pwm0_0@7020c10 {
|
|
compatible = "allwinner,sunxi-pwm20";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7020c10 0x00 0x04>;
|
|
reg_base = <0x7020c00>;
|
|
status = "disabled";
|
|
phandle = <0xae>;
|
|
};
|
|
|
|
s_pwm0_1@7020c11 {
|
|
compatible = "allwinner,sunxi-pwm21";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7020c11 0x00 0x04>;
|
|
reg_base = <0x7020c00>;
|
|
status = "disabled";
|
|
phandle = <0xaf>;
|
|
};
|
|
|
|
mcu_pwm0@7103000 {
|
|
#pwm-cells = <0x03>;
|
|
compatible = "allwinner,sunxi-pwm-v202";
|
|
reg = <0x00 0x7103000 0x00 0x400>;
|
|
clocks = <0x78 0x2b 0x78 0x2c>;
|
|
interrupts = <0x00 0xcf 0x04>;
|
|
clock-names = "clk_pwm\0clk_bus_pwm";
|
|
resets = <0x78 0x13>;
|
|
pwm-number = <0x08>;
|
|
pwm-base = <0x16>;
|
|
sunxi-pwms = <0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7>;
|
|
status = "disabled";
|
|
phandle = <0x1ae>;
|
|
};
|
|
|
|
mcu_pwm0_0@7103010 {
|
|
compatible = "allwinner,sunxi-pwm22";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7103010 0x00 0x04>;
|
|
reg_base = <0x7103000>;
|
|
status = "disabled";
|
|
phandle = <0xb0>;
|
|
};
|
|
|
|
mcu_pwm0_1@7103020 {
|
|
compatible = "allwinner,sunxi-pwm23";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7103020 0x00 0x04>;
|
|
reg_base = <0x7103000>;
|
|
status = "disabled";
|
|
phandle = <0xb1>;
|
|
};
|
|
|
|
mcu_pwm0_2@7103030 {
|
|
compatible = "allwinner,sunxi-pwm24";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7103030 0x00 0x04>;
|
|
reg_base = <0x7103000>;
|
|
status = "disabled";
|
|
phandle = <0xb2>;
|
|
};
|
|
|
|
mcu_pwm0_3@7103040 {
|
|
compatible = "allwinner,sunxi-pwm25";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7103040 0x00 0x04>;
|
|
reg_base = <0x7103000>;
|
|
status = "disabled";
|
|
phandle = <0xb3>;
|
|
};
|
|
|
|
mcu_pwm0_4@7103050 {
|
|
compatible = "allwinner,sunxi-pwm26";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7103050 0x00 0x04>;
|
|
reg_base = <0x7103000>;
|
|
status = "disabled";
|
|
phandle = <0xb4>;
|
|
};
|
|
|
|
mcu_pwm0_5@7103060 {
|
|
compatible = "allwinner,sunxi-pwm27";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7103060 0x00 0x04>;
|
|
reg_base = <0x7103000>;
|
|
status = "disabled";
|
|
phandle = <0xb5>;
|
|
};
|
|
|
|
mcu_pwm0_6@7103070 {
|
|
compatible = "allwinner,sunxi-pwm28";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7103070 0x00 0x04>;
|
|
reg_base = <0x7103000>;
|
|
status = "disabled";
|
|
phandle = <0xb6>;
|
|
};
|
|
|
|
mcu_pwm0_7@7103080 {
|
|
compatible = "allwinner,sunxi-pwm29";
|
|
pinctrl-names = "active\0sleep";
|
|
reg = <0x00 0x7103080 0x00 0x04>;
|
|
reg_base = <0x7103000>;
|
|
status = "disabled";
|
|
phandle = <0xb7>;
|
|
};
|
|
|
|
ledc@2008000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-leds";
|
|
reg = <0x00 0x2008000 0x00 0x400>;
|
|
interrupts = <0x00 0x1c 0x04>;
|
|
clocks = <0x1a 0xac 0x1a 0xad>;
|
|
clock-names = "clk_ledc\0clk_cpuapb";
|
|
resets = <0x1a 0x4a>;
|
|
reset-names = "ledc_reset";
|
|
dmas = <0xb8 0x2a 0xb8 0x2a>;
|
|
dma-names = "rx\0tx";
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xb9>;
|
|
pinctrl-1 = <0xba>;
|
|
led_count = <0x22>;
|
|
output_mode = "GRB";
|
|
reset_ns = <0x54>;
|
|
t1h_ns = <0x320>;
|
|
t1l_ns = <0x140>;
|
|
t0h_ns = <0x12c>;
|
|
t0l_ns = <0x320>;
|
|
wait_time0_ns = <0x54>;
|
|
wait_time1_ns = <0x54>;
|
|
wait_data_time_ns = <0x927c0>;
|
|
phandle = <0x1af>;
|
|
};
|
|
|
|
irrx@2005000 {
|
|
compatible = "allwinner,irrx";
|
|
reg = <0x00 0x2005000 0x00 0x400>;
|
|
interrupts = <0x00 0x1b 0x04>;
|
|
clocks = <0x1a 0x80 0x22 0x1a 0x7f>;
|
|
clock-names = "bus\0pclk\0mclk";
|
|
resets = <0x1a 0x2b>;
|
|
status = "okay";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xbb>;
|
|
pinctrl-1 = <0xbc>;
|
|
phandle = <0x1b0>;
|
|
};
|
|
|
|
s_irrx@7040000 {
|
|
compatible = "allwinner,irrx";
|
|
reg = <0x00 0x7040000 0x00 0x400>;
|
|
interrupts = <0x00 0xa7 0x04>;
|
|
clocks = <0x19 0x19 0x22 0x19 0x18>;
|
|
clock-names = "bus\0pclk\0mclk";
|
|
resets = <0x19 0x0d>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xbd>;
|
|
pinctrl-1 = <0xbe>;
|
|
phandle = <0x1b1>;
|
|
};
|
|
|
|
irtx@2003000 {
|
|
compatible = "allwinner,irtx";
|
|
reg = <0x00 0x2003000 0x00 0x400>;
|
|
interrupts = <0x00 0x1a 0x04>;
|
|
clocks = <0x1a 0x82 0x22 0x1a 0x81>;
|
|
clock-names = "bus\0pclk\0mclk";
|
|
resets = <0x1a 0x2c>;
|
|
status = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xbf>;
|
|
pinctrl-1 = <0xc0>;
|
|
phandle = <0x1b2>;
|
|
};
|
|
|
|
twi0@2502000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi0";
|
|
reg = <0x00 0x2502000 0x00 0x400>;
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
clocks = <0x1a 0x72>;
|
|
clock-names = "bus";
|
|
resets = <0x1a 0x24>;
|
|
dmas = <0xb8 0x2b 0xb8 0x2b>;
|
|
dma-names = "tx\0rx";
|
|
status = "okay";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0xc1>;
|
|
pinctrl-1 = <0xc2>;
|
|
pinctrl-names = "default\0sleep";
|
|
twi_drv_used = <0x01>;
|
|
phandle = <0x1b3>;
|
|
|
|
eeprom@50 {
|
|
compatible = "atmel,24c16";
|
|
reg = <0x50>;
|
|
status = "okay";
|
|
};
|
|
|
|
pcie_usb_phy@74 {
|
|
compatible = "combphy,phy74";
|
|
reg = <0x74>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie_usb_phy@75 {
|
|
compatible = "combphy,phy75";
|
|
reg = <0x75>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
twi1@2502400 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi1";
|
|
reg = <0x00 0x2502400 0x00 0x400>;
|
|
interrupts = <0x00 0x0b 0x04>;
|
|
clocks = <0x1a 0x71>;
|
|
clock-names = "bus";
|
|
resets = <0x1a 0x23>;
|
|
dmas = <0xb8 0x2c 0xb8 0x2c>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0xc3>;
|
|
pinctrl-1 = <0xc4>;
|
|
pinctrl-names = "default\0sleep";
|
|
twi_drv_used = <0x01>;
|
|
phandle = <0x1b4>;
|
|
};
|
|
|
|
twi2@2502800 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi2";
|
|
reg = <0x00 0x2502800 0x00 0x400>;
|
|
interrupts = <0x00 0x0c 0x04>;
|
|
clocks = <0x1a 0x70>;
|
|
clock-names = "bus";
|
|
resets = <0x1a 0x22>;
|
|
dmas = <0xb8 0x2d 0xb8 0x2d>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x1b5>;
|
|
};
|
|
|
|
twi3@2502c00 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi3";
|
|
reg = <0x00 0x2502c00 0x00 0x400>;
|
|
interrupts = <0x00 0x0d 0x04>;
|
|
clocks = <0x1a 0x6f>;
|
|
clock-names = "bus";
|
|
resets = <0x1a 0x21>;
|
|
dmas = <0xb8 0x2e 0xb8 0x2e>;
|
|
dma-names = "tx\0rx";
|
|
status = "okay";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0xc5>;
|
|
pinctrl-1 = <0xc6>;
|
|
pinctrl-names = "default\0sleep";
|
|
no_suspend = <0x01>;
|
|
twi_drv_used = <0x01>;
|
|
phandle = <0x1b6>;
|
|
|
|
ctp@0 {
|
|
compatible = "allwinner,goodix";
|
|
reg = <0x14>;
|
|
device_type = "ctp";
|
|
status = "okay";
|
|
ctp_name = "gt9xxnew_ts";
|
|
ctp_twi_id = <0x03>;
|
|
ctp_twi_addr = <0x14>;
|
|
ctp_screen_max_y = <0x500>;
|
|
ctp_screen_max_x = <0x320>;
|
|
ctp_revert_y_flag = <0x01>;
|
|
ctp_exchange_x_y_flag = <0x01>;
|
|
ctp_int_port = <0x4b 0x04 0x0c 0x01>;
|
|
ctp_wakeup = <0x4b 0x04 0x0b 0x00>;
|
|
phandle = <0x1b7>;
|
|
};
|
|
};
|
|
|
|
twi4@2503000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi4";
|
|
reg = <0x00 0x2503000 0x00 0x400>;
|
|
interrupts = <0x00 0x0e 0x04>;
|
|
clocks = <0x1a 0x6e>;
|
|
clock-names = "bus";
|
|
resets = <0x1a 0x20>;
|
|
dmas = <0xb8 0x2f 0xb8 0x2f>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0xc7>;
|
|
pinctrl-1 = <0xc8>;
|
|
pinctrl-names = "default\0sleep";
|
|
twi_drv_used = <0x01>;
|
|
phandle = <0x1b8>;
|
|
};
|
|
|
|
twi5@2503400 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi5";
|
|
reg = <0x00 0x2503400 0x00 0x400>;
|
|
interrupts = <0x00 0x0f 0x04>;
|
|
clocks = <0x1a 0x6d>;
|
|
clock-names = "bus";
|
|
resets = <0x1a 0x1f>;
|
|
dmas = <0xb8 0x30 0xb8 0x30>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0xc9>;
|
|
pinctrl-1 = <0xca>;
|
|
pinctrl-names = "default\0sleep";
|
|
twi_drv_used = <0x01>;
|
|
phandle = <0x1b9>;
|
|
};
|
|
|
|
s_twi0@7081400 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi6";
|
|
reg = <0x00 0x7081400 0x00 0x400>;
|
|
interrupts = <0x00 0xa4 0x04>;
|
|
clocks = <0x19 0x13>;
|
|
clock-names = "bus";
|
|
resets = <0x19 0x0a>;
|
|
dmas = <0xcb 0x09 0xcb 0x09>;
|
|
dma-names = "tx\0rx";
|
|
status = "okay";
|
|
clock-frequency = <0x61a80>;
|
|
pinctrl-0 = <0xcc>;
|
|
pinctrl-1 = <0xcd>;
|
|
pinctrl-names = "default\0sleep";
|
|
twi_drv_used = <0x01>;
|
|
no_suspend = <0x01>;
|
|
phandle = <0x1ba>;
|
|
|
|
axp1530@36 {
|
|
compatible = "ext,axp1530";
|
|
status = "okay";
|
|
reg = <0x36>;
|
|
wakeup-source;
|
|
phandle = <0x1bb>;
|
|
|
|
regulators {
|
|
|
|
dcdc1 {
|
|
regulator-name = "axp1530-dcdc1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x33e140>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-always-on;
|
|
phandle = <0x08>;
|
|
};
|
|
|
|
dcdc2 {
|
|
regulator-name = "axp1530-dcdc2";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x177fa0>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-ramp-delay = <0xc8>;
|
|
regulator-always-on;
|
|
phandle = <0xce>;
|
|
};
|
|
|
|
dcdc3 {
|
|
regulator-name = "axp1530-dcdc3";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x1c1380>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-always-on;
|
|
phandle = <0xcf>;
|
|
};
|
|
|
|
ldo1 {
|
|
regulator-name = "axp1530-aldo1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xd0>;
|
|
};
|
|
|
|
ldo2 {
|
|
regulator-name = "axp1530-dldo1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-step-delay-us = <0x19>;
|
|
regulator-final-delay-us = <0x32>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xd1>;
|
|
};
|
|
};
|
|
|
|
virtual-ext-dcdc1 {
|
|
compatible = "xpower-vregulator,ext-dcdc1";
|
|
dcdc1-supply = <0x08>;
|
|
};
|
|
|
|
virtual-ext-dcdc2 {
|
|
compatible = "xpower-vregulator,ext-dcdc2";
|
|
dcdc2-supply = <0xce>;
|
|
};
|
|
|
|
virtual-ext-dcdc3 {
|
|
compatible = "xpower-vregulator,ext-dcdc3";
|
|
dcdc3-supply = <0xcf>;
|
|
};
|
|
|
|
virtual-ext-aldo1 {
|
|
compatible = "xpower-vregulator,ext-aldo1";
|
|
aldo1-supply = <0xd0>;
|
|
};
|
|
|
|
virtual-ext-dldo1 {
|
|
compatible = "xpower-vregulator,ext-dldo1";
|
|
dldo1-supply = <0xd1>;
|
|
};
|
|
};
|
|
|
|
pmu@35 {
|
|
compatible = "x-powers,axp2202";
|
|
reg = <0x35>;
|
|
status = "okay";
|
|
interrupts = <0x00 0x08>;
|
|
interrupt-parent = <0xd2>;
|
|
x-powers,drive-vbus-en;
|
|
pmu_reset = <0x00>;
|
|
pmu_irq_wakeup = <0x01>;
|
|
pmu_hot_shutdown = <0x01>;
|
|
wakeup-source;
|
|
phandle = <0x1bc>;
|
|
|
|
usb_power_supply {
|
|
compatible = "x-powers,axp2202-usb-power-supply";
|
|
status = "okay";
|
|
pmu_usbpc_vol = <0x11f8>;
|
|
pmu_usbpc_cur = <0x1f4>;
|
|
pmu_usbad_vol = <0xfa0>;
|
|
pmu_usbad_cur = <0x9c4>;
|
|
pmu_usb_typec_used = <0x00>;
|
|
wakeup_usb_in;
|
|
wakeup_usb_out;
|
|
det_acin_supply = <0xd3>;
|
|
pmu_acin_usbid_drv = <0x4b 0x07 0x0c 0x01>;
|
|
pmu_vbus_det_gpio = <0x4b 0x07 0x0d 0x01>;
|
|
phandle = <0xd4>;
|
|
};
|
|
|
|
gpio_power_supply {
|
|
compatible = "x-powers,gpio-supply";
|
|
status = "disabled";
|
|
pmu_acin_det_gpio = <0x4b 0x07 0x0e 0x01>;
|
|
det_usb_supply = <0xd4>;
|
|
phandle = <0xd3>;
|
|
};
|
|
|
|
bat-power-supply {
|
|
compatible = "x-powers,axp2202-bat-power-supply";
|
|
param = <0xd5>;
|
|
status = "disabled";
|
|
pmu_chg_ic_temp = <0x00>;
|
|
pmu_battery_rdc = <0xaa>;
|
|
pmu_battery_cap = <0x1388>;
|
|
pmu_runtime_chgcur = <0x3e8>;
|
|
pmu_suspend_chgcur = <0x5dc>;
|
|
pmu_shutdown_chgcur = <0x5dc>;
|
|
pmu_init_chgvol = <0x10fe>;
|
|
pmu_battery_warning_level1 = <0x0f>;
|
|
pmu_battery_warning_level2 = <0x00>;
|
|
pmu_chgled_func = <0x00>;
|
|
pmu_chgled_type = <0x00>;
|
|
pmu_bat_para1 = <0x00>;
|
|
pmu_bat_para2 = <0x00>;
|
|
pmu_bat_para3 = <0x00>;
|
|
pmu_bat_para4 = <0x00>;
|
|
pmu_bat_para5 = <0x00>;
|
|
pmu_bat_para6 = <0x00>;
|
|
pmu_bat_para7 = <0x02>;
|
|
pmu_bat_para8 = <0x03>;
|
|
pmu_bat_para9 = <0x04>;
|
|
pmu_bat_para10 = <0x06>;
|
|
pmu_bat_para11 = <0x09>;
|
|
pmu_bat_para12 = <0x0e>;
|
|
pmu_bat_para13 = <0x1a>;
|
|
pmu_bat_para14 = <0x26>;
|
|
pmu_bat_para15 = <0x31>;
|
|
pmu_bat_para16 = <0x34>;
|
|
pmu_bat_para17 = <0x38>;
|
|
pmu_bat_para18 = <0x3c>;
|
|
pmu_bat_para19 = <0x40>;
|
|
pmu_bat_para20 = <0x46>;
|
|
pmu_bat_para21 = <0x4d>;
|
|
pmu_bat_para22 = <0x53>;
|
|
pmu_bat_para23 = <0x57>;
|
|
pmu_bat_para24 = <0x5a>;
|
|
pmu_bat_para25 = <0x5f>;
|
|
pmu_bat_para26 = <0x63>;
|
|
pmu_bat_para27 = <0x63>;
|
|
pmu_bat_para28 = <0x64>;
|
|
pmu_bat_para29 = <0x64>;
|
|
pmu_bat_para30 = <0x64>;
|
|
pmu_bat_para31 = <0x64>;
|
|
pmu_bat_para32 = <0x64>;
|
|
pmu_bat_temp_enable = <0x00>;
|
|
pmu_jetia_en = <0x00>;
|
|
pmu_bat_charge_ltf = <0x69f>;
|
|
pmu_bat_charge_htf = <0x97>;
|
|
pmu_bat_shutdown_ltf = <0x84d>;
|
|
pmu_bat_shutdown_htf = <0x83>;
|
|
pmu_jetia_cool = <0x551>;
|
|
pmu_jetia_warm = <0xd0>;
|
|
pmu_jcool_ifall = <0x00>;
|
|
pmu_jwarm_ifall = <0x00>;
|
|
pmu_bat_temp_para1 = <0x111a>;
|
|
pmu_bat_temp_para2 = <0xa7a>;
|
|
pmu_bat_temp_para3 = <0x84d>;
|
|
pmu_bat_temp_para4 = <0x69f>;
|
|
pmu_bat_temp_para5 = <0x551>;
|
|
pmu_bat_temp_para6 = <0x44d>;
|
|
pmu_bat_temp_para7 = <0x380>;
|
|
pmu_bat_temp_para8 = <0x25c>;
|
|
pmu_bat_temp_para9 = <0x1a0>;
|
|
pmu_bat_temp_para10 = <0x124>;
|
|
pmu_bat_temp_para11 = <0xf6>;
|
|
pmu_bat_temp_para12 = <0xd0>;
|
|
pmu_bat_temp_para13 = <0xb1>;
|
|
pmu_bat_temp_para14 = <0x97>;
|
|
pmu_bat_temp_para15 = <0x6f>;
|
|
pmu_bat_temp_para16 = <0x53>;
|
|
wakeup_bat_out;
|
|
wakeup_bat_untemp_work;
|
|
wakeup_bat_ovtemp_work;
|
|
phandle = <0x1bd>;
|
|
};
|
|
|
|
powerkey@0 {
|
|
status = "okay";
|
|
compatible = "x-powers,axp2101-pek";
|
|
pmu_powkey_off_time = <0x1770>;
|
|
pmu_powkey_off_func = <0x00>;
|
|
pmu_powkey_off_en = <0x01>;
|
|
pmu_powkey_long_time = <0x5dc>;
|
|
pmu_powkey_on_time = <0x200>;
|
|
wakeup_rising;
|
|
wakeup_falling;
|
|
phandle = <0x1be>;
|
|
};
|
|
|
|
regulators@0 {
|
|
phandle = <0x1bf>;
|
|
|
|
dcdc1 {
|
|
regulator-name = "axp2202-dcdc1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x177fa0>;
|
|
regulator-ramp-delay = <0xfa>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0x06>;
|
|
};
|
|
|
|
dcdc2 {
|
|
regulator-name = "axp2202-dcdc2";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x33e140>;
|
|
regulator-ramp-delay = <0xfa>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0x20>;
|
|
};
|
|
|
|
dcdc3 {
|
|
regulator-name = "axp2202-dcdc3";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x1c1380>;
|
|
regulator-ramp-delay = <0xfa>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-always-on;
|
|
phandle = <0xd6>;
|
|
};
|
|
|
|
dcdc4 {
|
|
regulator-name = "axp2202-dcdc4";
|
|
regulator-min-microvolt = <0xf4240>;
|
|
regulator-max-microvolt = <0x387520>;
|
|
regulator-ramp-delay = <0xfa>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xd7>;
|
|
};
|
|
|
|
rtcldo {
|
|
regulator-name = "axp2202-rtcldo";
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xd8>;
|
|
};
|
|
|
|
aldo1 {
|
|
regulator-name = "axp2202-aldo1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xd9>;
|
|
};
|
|
|
|
aldo2 {
|
|
regulator-name = "axp2202-aldo2";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xda>;
|
|
};
|
|
|
|
aldo3 {
|
|
regulator-name = "axp2202-aldo3";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
phandle = <0xdb>;
|
|
};
|
|
|
|
aldo4 {
|
|
regulator-name = "axp2202-aldo4";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
phandle = <0xdc>;
|
|
};
|
|
|
|
bldo1 {
|
|
regulator-name = "axp2202-bldo1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xdd>;
|
|
};
|
|
|
|
bldo2 {
|
|
regulator-name = "axp2202-bldo2";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xde>;
|
|
};
|
|
|
|
bldo3 {
|
|
regulator-name = "axp2202-bldo3";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0x56>;
|
|
};
|
|
|
|
bldo4 {
|
|
regulator-name = "axp2202-bldo4";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xdf>;
|
|
};
|
|
|
|
cldo1 {
|
|
regulator-name = "axp2202-cldo1";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0x4a>;
|
|
};
|
|
|
|
cldo2 {
|
|
regulator-name = "axp2202-cldo2";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xe0>;
|
|
};
|
|
|
|
cldo3 {
|
|
regulator-name = "axp2202-cldo3";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-ramp-delay = <0x9c4>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0x65>;
|
|
};
|
|
|
|
cldo4 {
|
|
regulator-name = "axp2202-cldo4";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x3567e0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0x49>;
|
|
};
|
|
|
|
cpusldo {
|
|
regulator-name = "axp2202-cpusldo";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x155cc0>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
phandle = <0xe1>;
|
|
};
|
|
|
|
vmid {
|
|
regulator-name = "axp2202-vmid";
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
phandle = <0x51>;
|
|
};
|
|
|
|
drivevbus {
|
|
regulator-name = "axp2202-drivevbus";
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
drivevbusin-supply = <0x51>;
|
|
phandle = <0xe2>;
|
|
};
|
|
};
|
|
|
|
virtual-dcdc1 {
|
|
compatible = "xpower-vregulator,dcdc1";
|
|
dcdc1-supply = <0x06>;
|
|
};
|
|
|
|
virtual-dcdc2 {
|
|
compatible = "xpower-vregulator,dcdc2";
|
|
dcdc2-supply = <0x20>;
|
|
};
|
|
|
|
virtual-dcdc3 {
|
|
compatible = "xpower-vregulator,dcdc3";
|
|
dcdc3-supply = <0xd6>;
|
|
};
|
|
|
|
virtual-dcdc4 {
|
|
compatible = "xpower-vregulator,dcdc4";
|
|
dcdc4-supply = <0xd7>;
|
|
};
|
|
|
|
virtual-rtcldo {
|
|
compatible = "xpower-vregulator,rtcldo";
|
|
rtcldo-supply = <0xd8>;
|
|
};
|
|
|
|
virtual-aldo1 {
|
|
compatible = "xpower-vregulator,aldo1";
|
|
aldo1-supply = <0xd9>;
|
|
};
|
|
|
|
virtual-aldo2 {
|
|
compatible = "xpower-vregulator,aldo2";
|
|
aldo2-supply = <0xda>;
|
|
};
|
|
|
|
virtual-aldo3 {
|
|
compatible = "xpower-vregulator,aldo3";
|
|
aldo3-supply = <0xdb>;
|
|
};
|
|
|
|
virtual-aldo4 {
|
|
compatible = "xpower-vregulator,aldo4";
|
|
aldo4-supply = <0xdc>;
|
|
};
|
|
|
|
virtual-bldo1 {
|
|
compatible = "xpower-vregulator,bldo1";
|
|
bldo1-supply = <0xdd>;
|
|
};
|
|
|
|
virtual-bldo2 {
|
|
compatible = "xpower-vregulator,bldo2";
|
|
bldo2-supply = <0xde>;
|
|
};
|
|
|
|
virtual-bldo3 {
|
|
compatible = "xpower-vregulator,bldo3";
|
|
bldo3-supply = <0x56>;
|
|
};
|
|
|
|
virtual-bldo4 {
|
|
compatible = "xpower-vregulator,bldo4";
|
|
bldo4-supply = <0xdf>;
|
|
};
|
|
|
|
virtual-cldo1 {
|
|
compatible = "xpower-vregulator,cldo1";
|
|
cldo1-supply = <0x4a>;
|
|
};
|
|
|
|
virtual-cldo2 {
|
|
compatible = "xpower-vregulator,cldo2";
|
|
cldo2-supply = <0xe0>;
|
|
};
|
|
|
|
virtual-cldo3 {
|
|
compatible = "xpower-vregulator,cldo3";
|
|
cldo3-supply = <0x65>;
|
|
};
|
|
|
|
virtual-cldo4 {
|
|
compatible = "xpower-vregulator,cldo4";
|
|
cldo4-supply = <0x49>;
|
|
};
|
|
|
|
virtual-cpusldo {
|
|
compatible = "xpower-vregulator,cpusldo";
|
|
cpusldo-supply = <0xe1>;
|
|
};
|
|
|
|
virtual-drivevbus {
|
|
compatible = "xpower-vregulator,drivevbus";
|
|
drivevbus-supply = <0xe2>;
|
|
};
|
|
|
|
axp_gpio@0 {
|
|
gpio-controller;
|
|
#size-cells = <0x00>;
|
|
#gpio-cells = <0x06>;
|
|
status = "okay";
|
|
phandle = <0x1c0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
s_twi1@7081800 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi7";
|
|
reg = <0x00 0x7081800 0x00 0x400>;
|
|
interrupts = <0x00 0xa5 0x04>;
|
|
clocks = <0x19 0x12>;
|
|
clock-names = "bus";
|
|
resets = <0x19 0x09>;
|
|
dmas = <0xcb 0x0a 0xcb 0x0a>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x1c1>;
|
|
};
|
|
|
|
s_twi2@7081c00 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-twi-v101";
|
|
device_type = "twi8";
|
|
reg = <0x00 0x7081c00 0x00 0x400>;
|
|
interrupts = <0x00 0x9c 0x04>;
|
|
clocks = <0x19 0x11>;
|
|
clock-names = "bus";
|
|
resets = <0x19 0x08>;
|
|
dmas = <0xcb 0x0e 0xcb 0x0e>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x1c2>;
|
|
};
|
|
|
|
spi@4025000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-spi-v1.3";
|
|
device_type = "spi0";
|
|
reg = <0x00 0x4025000 0x00 0x1000>;
|
|
interrupts = <0x00 0x10 0x04>;
|
|
clocks = <0x1a 0x08 0x1a 0x73 0x1a 0x7a>;
|
|
clock-names = "pll\0mod\0bus";
|
|
resets = <0x1a 0x28>;
|
|
dmas = <0xb8 0x16 0xb8 0x16>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x1c3>;
|
|
};
|
|
|
|
spi@4026000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-spi-v1.4";
|
|
device_type = "spi1";
|
|
reg = <0x00 0x4026000 0x00 0x1000>;
|
|
interrupts = <0x00 0x11 0x04>;
|
|
clocks = <0x1a 0x08 0x1a 0x74 0x1a 0x79>;
|
|
clock-names = "pll\0mod\0bus";
|
|
resets = <0x1a 0x27>;
|
|
dmas = <0xb8 0x17 0xb8 0x17>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x5f5e100>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xe3>;
|
|
pinctrl-1 = <0xe4>;
|
|
sunxi,spi-num-cs = <0x01>;
|
|
sunxi,spi-bus-mode = <0x01>;
|
|
sunxi,spi-cs-mode = <0x00>;
|
|
phandle = <0x1c4>;
|
|
|
|
spidev@0 {
|
|
reg = <0x00>;
|
|
compatible = "rohm,dh2228fv";
|
|
spi-max-frequency = <0x7a120>;
|
|
spi-rx-bus-width = <0x01>;
|
|
spi-tx-bus-width = <0x01>;
|
|
};
|
|
};
|
|
|
|
spi@4027000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-spi-v1.3";
|
|
device_type = "spi2";
|
|
reg = <0x00 0x4027000 0x00 0x1000>;
|
|
interrupts = <0x00 0x12 0x04>;
|
|
clocks = <0x1a 0x08 0x1a 0x75 0x1a 0x78>;
|
|
clock-names = "pll\0mod\0bus";
|
|
resets = <0x1a 0x26>;
|
|
dmas = <0xb8 0x18 0xb8 0x18>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
clock-frequency = <0x5f5e100>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xe5>;
|
|
pinctrl-1 = <0xe6>;
|
|
sunxi,spi-num-cs = <0x01>;
|
|
sunxi,spi-bus-mode = <0x01>;
|
|
sunxi,spi-cs-mode = <0x00>;
|
|
phandle = <0x1c5>;
|
|
|
|
spidev@0 {
|
|
reg = <0x00>;
|
|
compatible = "rohm,dh2228fv";
|
|
spi-max-frequency = <0x7a120>;
|
|
spi-rx-bus-width = <0x01>;
|
|
spi-tx-bus-width = <0x01>;
|
|
};
|
|
};
|
|
|
|
spi@7092000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-spi-v1.3";
|
|
device_type = "r_spi0";
|
|
reg = <0x00 0x7092000 0x00 0x1000>;
|
|
interrupts = <0x00 0xac 0x04>;
|
|
clocks = <0x1a 0x08 0x19 0x0b 0x19 0x0c>;
|
|
clock-names = "pll\0mod\0bus";
|
|
resets = <0x19 0x03>;
|
|
dmas = <0xcb 0x0d 0xcb 0x0d>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x1c6>;
|
|
};
|
|
|
|
spif@47f0000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sun55i-spif";
|
|
device_type = "spif";
|
|
reg = <0x00 0x47f0000 0x00 0x1000>;
|
|
interrupts = <0x00 0x14 0x04>;
|
|
clocks = <0x1a 0x07 0x1a 0x76 0x1a 0x77>;
|
|
clock-names = "pclk\0mclk\0bus";
|
|
resets = <0x1a 0x25>;
|
|
status = "disabled";
|
|
phandle = <0x1c7>;
|
|
};
|
|
|
|
nand0@4011000 {
|
|
compatible = "allwinner,sun55iw3-nand";
|
|
device_type = "nand0";
|
|
reg = <0x00 0x4011000 0x00 0x1000>;
|
|
interrupts = <0x00 0x26 0x04>;
|
|
clocks = <0x1a 0x13 0x1a 0x5c 0x1a 0x5d 0x1a 0x5b 0x1a 0x56>;
|
|
clock-names = "pll_periph\0mclk\0ecc\0bus\0mbus";
|
|
resets = <0x1a 0x12>;
|
|
reset-names = "rst";
|
|
power-domains = <0x1f 0x06>;
|
|
nand0_regulator1 = "vcc-nand";
|
|
nand0_regulator2 = "none";
|
|
nand0_cache_level = <0x55aaaa55>;
|
|
nand0_flush_cache_num = <0x55aaaa55>;
|
|
nand0_capacity_level = <0x55aaaa55>;
|
|
nand0_id_number_ctl = <0x55aaaa55>;
|
|
nand0_print_level = <0x55aaaa55>;
|
|
nand0_p0 = <0x55aaaa55>;
|
|
nand0_p1 = <0x55aaaa55>;
|
|
nand0_p2 = <0x55aaaa55>;
|
|
nand0_p3 = <0x55aaaa55>;
|
|
chip_code = "sun55iw3";
|
|
status = "disabled";
|
|
boot_crc = "disabled";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xe7 0xe8>;
|
|
pinctrl-1 = <0xe9>;
|
|
phandle = <0x1c8>;
|
|
};
|
|
|
|
lradc@2009800 {
|
|
compatible = "allwinner,keyboard_1350mv";
|
|
reg = <0x00 0x2009800 0x00 0x100>;
|
|
interrupts = <0x00 0x42 0x04>;
|
|
clocks = <0x1a 0x93>;
|
|
resets = <0x1a 0x38>;
|
|
status = "okay";
|
|
key_cnt = <0x02>;
|
|
key0 = <0x286 0x73>;
|
|
key1 = <0x384 0x72>;
|
|
key_debounce;
|
|
debounce_value = <0x96>;
|
|
phandle = <0x1c9>;
|
|
};
|
|
|
|
nsi-controller@2020000 {
|
|
compatible = "allwinner,sun55i-nsi";
|
|
interrupts = <0x00 0x2b 0x04>;
|
|
reg = <0x00 0x2020000 0x00 0x10000 0x00 0x2071000 0x00 0x400>;
|
|
clocks = <0x1a 0x00 0x1a 0x31>;
|
|
clock-names = "pll\0bus";
|
|
resets = <0x1a 0x00>;
|
|
clock-frequency = <0x1b898f80>;
|
|
#nsi-cells = <0x01>;
|
|
phandle = <0x1ca>;
|
|
|
|
npu {
|
|
id = <0x05>;
|
|
mode = <0x00>;
|
|
pri = <0x00>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
gmac0 {
|
|
id = <0x12>;
|
|
mode = <0x00>;
|
|
pri = <0x01>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
gmac1 {
|
|
id = <0x13>;
|
|
mode = <0x00>;
|
|
pri = <0x01>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
smhc0 {
|
|
id = <0x14>;
|
|
mode = <0x00>;
|
|
pri = <0x01>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
smhc1 {
|
|
id = <0x15>;
|
|
mode = <0x00>;
|
|
pri = <0x01>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
smhc2 {
|
|
id = <0x16>;
|
|
mode = <0x00>;
|
|
pri = <0x01>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
usb0 {
|
|
id = <0x17>;
|
|
mode = <0x00>;
|
|
pri = <0x01>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
usb1 {
|
|
id = <0x18>;
|
|
mode = <0x00>;
|
|
pri = <0x01>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
usb2 {
|
|
id = <0x19>;
|
|
mode = <0x00>;
|
|
pri = <0x01>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
isp {
|
|
id = <0x06>;
|
|
mode = <0x00>;
|
|
pri = <0x02>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
iommu {
|
|
id = <0x0a>;
|
|
mode = <0x00>;
|
|
pri = <0x03>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
ve_r {
|
|
id = <0x0b>;
|
|
mode = <0x00>;
|
|
pri = <0x02>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
ve_rw {
|
|
id = <0x0c>;
|
|
mode = <0x00>;
|
|
pri = <0x02>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
de {
|
|
id = <0x0d>;
|
|
mode = <0x00>;
|
|
pri = <0x02>;
|
|
select = <0x01>;
|
|
};
|
|
|
|
csi {
|
|
id = <0x0e>;
|
|
mode = <0x00>;
|
|
pri = <0x02>;
|
|
select = <0x01>;
|
|
};
|
|
};
|
|
|
|
npd@2070000 {
|
|
compatible = "allwinner,sun55i-npd";
|
|
status = "okay";
|
|
phandle = <0x1cb>;
|
|
};
|
|
|
|
ce@3040000 {
|
|
compatible = "allwinner,sunxi-ce";
|
|
device_name = "ce";
|
|
reg = <0x00 0x3040000 0x00 0xa0 0x00 0x3040800 0x00 0xa0>;
|
|
interrupts = <0x00 0x34 0x01 0x00 0x35 0x01>;
|
|
clock-frequency = <0x17d78400>;
|
|
clocks = <0x1a 0x3e 0x1a 0x3c 0x1a 0x57 0x1a 0x07 0x1a 0x3d>;
|
|
clock-names = "bus_ce\0ce_clk\0mbus_ce\0clk_src\0ce_sys_clk";
|
|
resets = <0x1a 0x07>;
|
|
phandle = <0x1cc>;
|
|
};
|
|
|
|
rtc@7090000 {
|
|
compatible = "allwinner,rtc-v201";
|
|
device_type = "rtc";
|
|
wakeup-source;
|
|
reg = <0x00 0x7090000 0x00 0x320>;
|
|
interrupts = <0x00 0x9d 0x04>;
|
|
clocks = <0x19 0x1b 0x23 0x07 0x23 0x09>;
|
|
clock-names = "r-ahb-rtc\0rtc-1k\0rtc-spi";
|
|
resets = <0x19 0x0e>;
|
|
gpr_cur_pos = <0x06>;
|
|
gpr_bootcount_pos = <0x07>;
|
|
phandle = <0x1cd>;
|
|
};
|
|
|
|
sdmmc@4022000 {
|
|
compatible = "allwinner,sunxi-mmc-v4p6x";
|
|
device_type = "sdc2";
|
|
reg = <0x00 0x4022000 0x00 0x1000>;
|
|
interrupts = <0x00 0x2a 0x04>;
|
|
clocks = <0x22 0x1a 0x10 0x1a 0x12 0x1a 0x60 0x1a 0x61>;
|
|
clock-names = "osc24m\0pll_periph\0pll_periph_2\0mmc\0ahb";
|
|
resets = <0x1a 0x13>;
|
|
reset-names = "rst";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xea 0xeb>;
|
|
pinctrl-1 = <0xec>;
|
|
bus-width = <0x08>;
|
|
req-page-count = <0x02>;
|
|
cap-mmc-highspeed;
|
|
cap-cmd23;
|
|
mmc-cache-ctrl;
|
|
non-removable;
|
|
max-frequency = <0x5f5e100>;
|
|
cap-erase;
|
|
mmc-high-capacity-erase-size;
|
|
no-sdio;
|
|
no-sd;
|
|
ctl-spec-caps = <0x328>;
|
|
sdc_tm4_sm0_freq0 = <0x00>;
|
|
sdc_tm4_sm0_freq1 = <0x00>;
|
|
sdc_tm4_sm1_freq0 = <0x00>;
|
|
sdc_tm4_sm1_freq1 = <0x00>;
|
|
sdc_tm4_sm2_freq0 = <0x00>;
|
|
sdc_tm4_sm2_freq1 = <0x00>;
|
|
sdc_tm4_sm3_freq0 = <0x5000000>;
|
|
sdc_tm4_sm3_freq1 = <0x05>;
|
|
sdc_tm4_sm4_freq0 = <0x50000>;
|
|
sdc_tm4_sm4_freq1 = <0x04>;
|
|
sdc_tm4_sm4_freq0_cmd = <0x00>;
|
|
sdc_tm4_sm4_freq1_cmd = <0x00>;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
sunxi-power-save-mode;
|
|
sunxi-dis-signal-vol-sw;
|
|
mmc-bootpart-noacc;
|
|
cqe-on;
|
|
ctl-cmdq-md = <0x02>;
|
|
vmmc-supply = <0x65>;
|
|
vqmmc-supply = <0x4a>;
|
|
status = "okay";
|
|
phandle = <0x1ce>;
|
|
};
|
|
|
|
sdmmc@4020000 {
|
|
compatible = "allwinner,sunxi-mmc-v5p3x";
|
|
device_type = "sdc0";
|
|
reg = <0x00 0x4020000 0x00 0x1000>;
|
|
interrupts = <0x00 0x28 0x04>;
|
|
clocks = <0x22 0x1a 0x13 0x1a 0x14 0x1a 0x5e 0x1a 0x63>;
|
|
clock-names = "osc24m\0pll_periph\0pll_periph_2\0mmc\0ahb";
|
|
resets = <0x1a 0x15>;
|
|
reset-names = "rst";
|
|
pinctrl-names = "default\0mmc_1v8\0sleep\0uart_jtag";
|
|
pinctrl-0 = <0xed>;
|
|
pinctrl-1 = <0xee>;
|
|
pinctrl-2 = <0xef>;
|
|
pinctrl-3 = <0xf0 0xf1>;
|
|
max-frequency = <0x8f0d180>;
|
|
bus-width = <0x04>;
|
|
req-page-count = <0x02>;
|
|
cap-sd-highspeed;
|
|
cap-wait-while-busy;
|
|
ctl-spec-caps = <0x428>;
|
|
status = "okay";
|
|
cd-gpios = <0x4b 0x05 0x06 0x11>;
|
|
cd-used-24M;
|
|
cd-set-debounce = <0x01>;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-ddr50;
|
|
sd-uhs-sdr104;
|
|
no-sdio;
|
|
no-mmc;
|
|
sunxi-power-save-mode;
|
|
vmmc-supply = <0x65>;
|
|
vqmmc33sw-supply = <0x65>;
|
|
vdmmc33sw-supply = <0x65>;
|
|
vqmmc18sw-supply = <0x4a>;
|
|
vdmmc18sw-supply = <0x4a>;
|
|
phandle = <0x1cf>;
|
|
};
|
|
|
|
sdmmc@4021000 {
|
|
compatible = "allwinner,sunxi-mmc-v5p3x";
|
|
device_type = "sdc1";
|
|
reg = <0x00 0x4021000 0x00 0x1000>;
|
|
interrupts = <0x00 0x29 0x04>;
|
|
clocks = <0x22 0x1a 0x13 0x1a 0x14 0x1a 0x5f 0x1a 0x62>;
|
|
clock-names = "osc24m\0pll_periph\0pll_periph_2\0mmc\0ahb";
|
|
resets = <0x1a 0x14>;
|
|
reset-names = "rst";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xf2>;
|
|
pinctrl-1 = <0xf3>;
|
|
max-frequency = <0xc65d400>;
|
|
bus-width = <0x04>;
|
|
cap-sd-highspeed;
|
|
cap-sdio-irq;
|
|
ignore-pm-notify;
|
|
keep-power-in-suspend;
|
|
sunxi-dly-208M = <0xff 0x01 0xff 0xff 0xff 0xff>;
|
|
ctl-spec-caps = <0x428>;
|
|
status = "okay";
|
|
no-mmc;
|
|
no-sd;
|
|
sd-uhs-sdr25;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-ddr50;
|
|
sd-uhs-sdr104;
|
|
sunxi-dis-signal-vol-sw;
|
|
phandle = <0x1d0>;
|
|
};
|
|
|
|
usbc0@10 {
|
|
device_type = "usbc0";
|
|
compatible = "allwinner,sunxi-otg-manager";
|
|
reg = <0x00 0x10 0x00 0x1000>;
|
|
usb_port_type = <0x02>;
|
|
usb_detect_type = <0x02>;
|
|
usb_detect_mode = <0x00>;
|
|
usb_id_gpio;
|
|
usb_det_vbus_gpio = "axp_ctrl";
|
|
usb_regulator_io = "nocare";
|
|
usb_wakeup_suspend = <0x01>;
|
|
usb_luns = <0x03>;
|
|
usb_serial_unique = <0x00>;
|
|
usb_serial_number = "20080411";
|
|
rndis_wceis = <0x01>;
|
|
status = "okay";
|
|
det_vbus_supply = <0xd4>;
|
|
wakeup-source;
|
|
phandle = <0x1d1>;
|
|
};
|
|
|
|
udc-controller@4100000 {
|
|
compatible = "allwinner,sunxi-udc";
|
|
reg = <0x00 0x4100000 0x00 0x1000 0x00 0x00 0x00 0x100>;
|
|
interrupts = <0x00 0x1d 0x04>;
|
|
clocks = <0x1a 0xb7 0x1a 0x8e>;
|
|
clock-names = "hosc\0bus_otg";
|
|
resets = <0x1a 0x33 0x1a 0x30>;
|
|
reset-names = "otg\0phy";
|
|
status = "okay";
|
|
det_vbus_supply = <0xd4>;
|
|
phandle = <0x1d2>;
|
|
};
|
|
|
|
ehci0-controller@4101000 {
|
|
compatible = "allwinner,sunxi-ehci0";
|
|
reg = <0x00 0x4101000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x4100000 0x00 0x1000>;
|
|
interrupts = <0x00 0x1e 0x04>;
|
|
clocks = <0x1a 0xb7 0x1a 0x90>;
|
|
clock-names = "hosc\0bus_hci";
|
|
resets = <0x1a 0x35 0x1a 0x30>;
|
|
reset-names = "hci\0phy";
|
|
hci_ctrl_no = <0x00>;
|
|
status = "okay";
|
|
drvvbus-supply = <0xe2>;
|
|
phandle = <0x1d3>;
|
|
};
|
|
|
|
ohci0-controller@4101400 {
|
|
compatible = "allwinner,sunxi-ohci0";
|
|
reg = <0x00 0x4101400 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x4100000 0x00 0x1000>;
|
|
interrupts = <0x00 0x1f 0x04>;
|
|
clocks = <0x1a 0xb7 0x1a 0x92 0x1a 0x89>;
|
|
clock-names = "hosc\0bus_hci\0ohci";
|
|
resets = <0x1a 0x37 0x1a 0x30>;
|
|
reset-names = "hci\0phy";
|
|
hci_ctrl_no = <0x00>;
|
|
status = "okay";
|
|
drvvbus-supply = <0xe2>;
|
|
phandle = <0x1d4>;
|
|
};
|
|
|
|
usbc1@11 {
|
|
device_type = "usbc1";
|
|
reg = <0x00 0x11 0x00 0x1000>;
|
|
usb_regulator_io = "nocare";
|
|
usb_wakeup_suspend = <0x01>;
|
|
status = "okay";
|
|
wakeup-source;
|
|
phandle = <0x1d5>;
|
|
};
|
|
|
|
ehci1-controller@4200000 {
|
|
compatible = "allwinner,sunxi-ehci1";
|
|
reg = <0x00 0x4200000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x4100000 0x00 0x1000>;
|
|
interrupts = <0x00 0x20 0x04>;
|
|
clocks = <0x1a 0xb7 0x1a 0x8f>;
|
|
clock-names = "hosc\0bus_hci";
|
|
resets = <0x1a 0x34 0x1a 0x31>;
|
|
reset-names = "hci\0phy";
|
|
hci_ctrl_no = <0x01>;
|
|
status = "okay";
|
|
drvvbus-supply = <0xf4>;
|
|
phandle = <0x1d6>;
|
|
};
|
|
|
|
ohci1-controller@4200400 {
|
|
compatible = "allwinner,sunxi-ohci1";
|
|
reg = <0x00 0x4200400 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x4100000 0x00 0x1000>;
|
|
interrupts = <0x00 0x21 0x04>;
|
|
clocks = <0x1a 0xb7 0x1a 0x91 0x1a 0x8a>;
|
|
clock-names = "hosc\0bus_hci\0ohci";
|
|
resets = <0x1a 0x36 0x1a 0x31>;
|
|
reset-names = "hci\0phy";
|
|
hci_ctrl_no = <0x01>;
|
|
status = "okay";
|
|
drvvbus-supply = <0xf4>;
|
|
phandle = <0x1d7>;
|
|
};
|
|
|
|
usbc2@12 {
|
|
device_type = "usbc2";
|
|
compatible = "allwinner,sunxi-plat-dwc3";
|
|
reg = <0x00 0x12 0x00 0x1000>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
ranges;
|
|
aw,hcgen2-phygen1-quirk;
|
|
status = "disabled";
|
|
phandle = <0x1d8>;
|
|
|
|
xhci2-controller@4d00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x00 0x4d00000 0x00 0x100000>;
|
|
interrupts = <0x00 0x23 0x04>;
|
|
dr_mode = "otg";
|
|
clocks = <0x1a 0x55 0x1a 0x8c 0x1a 0x8b 0x1a 0x8d>;
|
|
clock-names = "bus_clk\0ref_clk3\0ref_clk2\0suspend";
|
|
resets = <0x1a 0x32>;
|
|
reset-names = "hci";
|
|
maximum-speed = "super-speed";
|
|
phy_type = "utmi";
|
|
snps,dis_enblslpm_quirk;
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
snps,dis_u3_susphy_quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
phys = <0xf5 0xf6 0x04>;
|
|
phy-names = "usb2-phy\0usb3-phy";
|
|
status = "disabled";
|
|
phandle = <0x1d9>;
|
|
};
|
|
};
|
|
|
|
phy@4e00000 {
|
|
compatible = "allwinner,sunxi-plat-phy";
|
|
reg = <0x00 0x4e00000 0x00 0x800>;
|
|
#phy-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0xf5>;
|
|
};
|
|
|
|
vind@5800800 {
|
|
compatible = "allwinner,sunxi-vin-media\0simple-bus";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
ranges;
|
|
device_id = <0x00>;
|
|
csi_top = <0x15752a00>;
|
|
csi_isp = <0x11e1a300>;
|
|
reg = <0x00 0x5800800 0x00 0x200 0x00 0x5800000 0x00 0x800 0x00 0x5810000 0x00 0x100>;
|
|
interrupts = <0x00 0x8b 0x04>;
|
|
clocks = <0x1a 0xae 0x1a 0x23 0x1a 0xaf 0x22 0x1a 0x23 0x1a 0xb0 0x22 0x1a 0x23 0x1a 0xb1 0x22 0x1a 0x23 0x1a 0xb2 0x22 0x1a 0x23 0x1a 0xb4 0x1a 0x20 0x1a 0xb3 0x1a 0x54 0x1a 0x53>;
|
|
clock-names = "csi_top\0csi_top_src\0csi_mclk0\0csi_mclk0_24m\0csi_mclk0_pll\0csi_mclk1\0csi_mclk1_24m\0csi_mclk1_pll\0csi_mclk2\0csi_mclk2_24m\0csi_mclk2_pll\0csi_mclk3\0csi_mclk3_24m\0csi_mclk3_pll\0csi_isp\0csi_isp_src\0csi_bus\0csi_mbus\0csi_isp_mbus";
|
|
resets = <0x1a 0x4b 0x1a 0x4c>;
|
|
reset-names = "csi_ret\0isp_ret";
|
|
pinctrl-names = "mclk0-default\0mclk0-sleep\0mclk1-default\0mclk1-sleep\0mclk2-default\0mclk2-sleep\0mclk3-default\0mclk3-sleep";
|
|
pinctrl-0 = <0xf7>;
|
|
pinctrl-1 = <0xf8>;
|
|
pinctrl-2 = <0xf9>;
|
|
pinctrl-3 = <0xfa>;
|
|
pinctrl-4 = <0xfb>;
|
|
pinctrl-5 = <0xfc>;
|
|
pinctrl-6 = <0xfd>;
|
|
pinctrl-7 = <0xfe>;
|
|
power-domains = <0x1f 0x02>;
|
|
dram_dfs_time = <0x96>;
|
|
status = "okay";
|
|
vind_mclkpin-supply = <0xda>;
|
|
vind_mclkpin_vol = <0x1b7740>;
|
|
vind_mcsipin-supply = <0x4a>;
|
|
vind_mcsipin_vol = <0x1b7740>;
|
|
vind_mipipin-supply = <0x65>;
|
|
vind_mipipin_vol = <0x325aa0>;
|
|
phandle = <0x1da>;
|
|
|
|
csi@5820000 {
|
|
compatible = "allwinner,sunxi-csi";
|
|
reg = <0x00 0x5820000 0x00 0x1000>;
|
|
interrupts = <0x00 0x82 0x04>;
|
|
device_id = <0x00>;
|
|
status = "okay";
|
|
phandle = <0x1db>;
|
|
};
|
|
|
|
csi@5821000 {
|
|
compatible = "allwinner,sunxi-csi";
|
|
reg = <0x00 0x5821000 0x00 0x1000>;
|
|
interrupts = <0x00 0x83 0x04>;
|
|
device_id = <0x01>;
|
|
status = "okay";
|
|
phandle = <0x1dc>;
|
|
};
|
|
|
|
csi@5822000 {
|
|
compatible = "allwinner,sunxi-csi";
|
|
reg = <0x00 0x5822000 0x00 0x1000>;
|
|
interrupts = <0x00 0x84 0x04>;
|
|
device_id = <0x02>;
|
|
status = "okay";
|
|
phandle = <0x1dd>;
|
|
};
|
|
|
|
csi@5823000 {
|
|
compatible = "allwinner,sunxi-csi";
|
|
reg = <0x00 0x5823000 0x00 0x1000>;
|
|
interrupts = <0x00 0x93 0x04>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0xff>;
|
|
pinctrl-1 = <0x100>;
|
|
device_id = <0x03>;
|
|
status = "disabled";
|
|
phandle = <0x1de>;
|
|
};
|
|
|
|
mipi@5810100 {
|
|
compatible = "allwinner,sunxi-mipi";
|
|
reg = <0x00 0x5810100 0x00 0x100 0x00 0x5811000 0x00 0x400>;
|
|
interrupts = <0x00 0x89 0x04>;
|
|
pinctrl-names = "mipi0-default\0mipi0-sleep\0mipi1-4lane-default\0mipi1-4lane-sleep";
|
|
pinctrl-0 = <0x101>;
|
|
pinctrl-1 = <0x102>;
|
|
pinctrl-2 = <0x103>;
|
|
pinctrl-3 = <0x104>;
|
|
device_id = <0x00>;
|
|
status = "okay";
|
|
phandle = <0x1df>;
|
|
};
|
|
|
|
mipi@5810200 {
|
|
compatible = "allwinner,sunxi-mipi";
|
|
reg = <0x00 0x5810200 0x00 0x100 0x00 0x5811400 0x00 0x400>;
|
|
pinctrl-names = "mipi1-default\0mipi1-sleep";
|
|
pinctrl-0 = <0x105>;
|
|
pinctrl-1 = <0x106>;
|
|
device_id = <0x01>;
|
|
status = "okay";
|
|
phandle = <0x1e0>;
|
|
};
|
|
|
|
mipi@5810300 {
|
|
compatible = "allwinner,sunxi-mipi";
|
|
reg = <0x00 0x5810300 0x00 0x100 0x00 0x5811800 0x00 0x400>;
|
|
pinctrl-names = "mipi2-default\0mipi2-sleep\0mipi3-4lane-default\0mipi3-4lane-sleep";
|
|
pinctrl-0 = <0x107>;
|
|
pinctrl-1 = <0x108>;
|
|
pinctrl-2 = <0x109>;
|
|
pinctrl-3 = <0x10a>;
|
|
device_id = <0x02>;
|
|
status = "okay";
|
|
phandle = <0x1e1>;
|
|
};
|
|
|
|
mipi@5810400 {
|
|
compatible = "allwinner,sunxi-mipi";
|
|
reg = <0x00 0x5810400 0x00 0x100 0x00 0x5811c00 0x00 0x400>;
|
|
pinctrl-names = "mipi3-default\0mipi3-sleep";
|
|
pinctrl-0 = <0x10b>;
|
|
pinctrl-1 = <0x10c>;
|
|
device_id = <0x03>;
|
|
status = "okay";
|
|
phandle = <0x1e2>;
|
|
};
|
|
|
|
tdm@5908000 {
|
|
compatible = "allwinner,sunxi-tdm";
|
|
reg = <0x00 0x5908000 0x00 0x300>;
|
|
interrupts = <0x00 0x8a 0x04>;
|
|
work_mode = <0x00>;
|
|
device_id = <0x00>;
|
|
iommus = <0x1e 0x00 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1e3>;
|
|
};
|
|
|
|
isp@5900000 {
|
|
compatible = "allwinner,sunxi-isp";
|
|
reg = <0x00 0x5900000 0x00 0x1300>;
|
|
interrupts = <0x00 0x85 0x04>;
|
|
work_mode = <0x00>;
|
|
device_id = <0x00>;
|
|
iommus = <0x1e 0x00 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1e4>;
|
|
};
|
|
|
|
isp@58ffffc {
|
|
compatible = "allwinner,sunxi-isp";
|
|
reg = <0x00 0x58ffffc 0x00 0x1304>;
|
|
interrupts = <0x00 0x86 0x04>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x01>;
|
|
iommus = <0x1e 0x00 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1e5>;
|
|
};
|
|
|
|
isp@58ffff8 {
|
|
compatible = "allwinner,sunxi-isp";
|
|
reg = <0x00 0x58ffff8 0x00 0x1308>;
|
|
interrupts = <0x00 0x87 0x04>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x02>;
|
|
iommus = <0x1e 0x00 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1e6>;
|
|
};
|
|
|
|
isp@58ffff4 {
|
|
compatible = "allwinner,sunxi-isp";
|
|
reg = <0x00 0x58ffff4 0x00 0x130c>;
|
|
interrupts = <0x00 0x88 0x04>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x03>;
|
|
iommus = <0x1e 0x00 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1e7>;
|
|
};
|
|
|
|
isp@4 {
|
|
compatible = "allwinner,sunxi-isp";
|
|
device_id = <0x04>;
|
|
iommus = <0x1e 0x00 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1e8>;
|
|
};
|
|
|
|
isp@5 {
|
|
compatible = "allwinner,sunxi-isp";
|
|
device_id = <0x05>;
|
|
iommus = <0x1e 0x00 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1e9>;
|
|
};
|
|
|
|
isp@6 {
|
|
compatible = "allwinner,sunxi-isp";
|
|
device_id = <0x06>;
|
|
iommus = <0x1e 0x00 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1ea>;
|
|
};
|
|
|
|
scaler@5910000 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x5910000 0x00 0x400>;
|
|
interrupts = <0x00 0x7e 0x04>;
|
|
work_mode = <0x00>;
|
|
device_id = <0x00>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1eb>;
|
|
};
|
|
|
|
scaler@590fffc {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x590fffc 0x00 0x404>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x01>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1ec>;
|
|
};
|
|
|
|
scaler@590fff8 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x590fff8 0x00 0x408>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x02>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1ed>;
|
|
};
|
|
|
|
scaler@590fff4 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x590fff4 0x00 0x40c>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x03>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1ee>;
|
|
};
|
|
|
|
scaler@5910400 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x5910400 0x00 0x400>;
|
|
interrupts = <0x00 0x7f 0x04>;
|
|
work_mode = <0x00>;
|
|
device_id = <0x04>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1ef>;
|
|
};
|
|
|
|
scaler@59103fc {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x59103fc 0x00 0x404>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x05>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1f0>;
|
|
};
|
|
|
|
scaler@59103f8 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x59103f8 0x00 0x408>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x06>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1f1>;
|
|
};
|
|
|
|
scaler@59103f4 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x59103f4 0x00 0x40c>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x07>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1f2>;
|
|
};
|
|
|
|
scaler@5910800 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x5910800 0x00 0x400>;
|
|
interrupts = <0x00 0x80 0x04>;
|
|
work_mode = <0x00>;
|
|
device_id = <0x08>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1f3>;
|
|
};
|
|
|
|
scaler@59107fc {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x59107fc 0x00 0x404>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x09>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1f4>;
|
|
};
|
|
|
|
scaler@59107f8 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x59107f8 0x00 0x408>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x0a>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1f5>;
|
|
};
|
|
|
|
scaler@59107f4 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x59107f4 0x00 0x40c>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x0b>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1f6>;
|
|
};
|
|
|
|
scaler@5910c00 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x5910c00 0x00 0x400>;
|
|
interrupts = <0x00 0x81 0x04>;
|
|
work_mode = <0x00>;
|
|
device_id = <0x0c>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1f7>;
|
|
};
|
|
|
|
scaler@5910bfc {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x5910bfc 0x00 0x404>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x0d>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1f8>;
|
|
};
|
|
|
|
scaler@5910bf8 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x5910bf8 0x00 0x408>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x0e>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1f9>;
|
|
};
|
|
|
|
scaler@5910bf4 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x00 0x5910bf4 0x00 0x40c>;
|
|
work_mode = <0xff>;
|
|
device_id = <0x0f>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x1fa>;
|
|
};
|
|
|
|
scaler@16 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
device_id = <0x10>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1fb>;
|
|
};
|
|
|
|
scaler@17 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
device_id = <0x11>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "okay";
|
|
phandle = <0x1fc>;
|
|
};
|
|
|
|
actuator@2108180 {
|
|
compatible = "allwinner,sunxi-actuator";
|
|
device_type = "actuator0";
|
|
reg = <0x00 0x2108180 0x00 0x10>;
|
|
actuator0_name = "dw9714_act";
|
|
actuator0_slave = <0x18>;
|
|
actuator0_af_pwdn;
|
|
actuator0_afvdd = "afvcc-csi";
|
|
actuator0_afvdd_vol = <0x325aa0>;
|
|
status = "disabled";
|
|
phandle = <0x10e>;
|
|
};
|
|
|
|
flash@2108190 {
|
|
device_type = "flash0";
|
|
compatible = "allwinner,sunxi-flash";
|
|
reg = <0x00 0x2108190 0x00 0x10>;
|
|
flash0_type = <0x02>;
|
|
flash0_en = <0x62 0x00 0x0b 0x01>;
|
|
flash0_mode;
|
|
flash0_flvdd = [00];
|
|
flash0_flvdd_vol;
|
|
device_id = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x10d>;
|
|
};
|
|
|
|
sensor@5812000 {
|
|
reg = <0x00 0x5812000 0x00 0x10>;
|
|
device_type = "sensor0";
|
|
compatible = "allwinner,sunxi-sensor";
|
|
sensor0_mname = "imx219";
|
|
sensor0_twi_cci_id = <0x00>;
|
|
sensor0_twi_addr = <0x20>;
|
|
sensor0_mclk_id = <0x02>;
|
|
sensor0_pos = "rear";
|
|
sensor0_isp_used = <0x01>;
|
|
sensor0_fmt = <0x01>;
|
|
sensor0_stby_mode = <0x00>;
|
|
sensor0_vflip = <0x00>;
|
|
sensor0_hflip = <0x00>;
|
|
sensor0_iovdd-supply = <0xda>;
|
|
sensor0_iovdd_vol = <0x1b7740>;
|
|
sensor0_avdd-supply = <0xd9>;
|
|
sensor0_avdd_vol = <0x2ab980>;
|
|
sensor0_dvdd-supply = <0xdf>;
|
|
sensor0_dvdd_vol = <0x16e360>;
|
|
sensor0_power_en;
|
|
sensor0_reset;
|
|
sensor0_pwdn = <0x4b 0x07 0x02 0x00>;
|
|
sensor0_sm_vs;
|
|
flash_handle = <0x10d>;
|
|
act_handle = <0x10e>;
|
|
device_id = <0x00>;
|
|
status = "okay";
|
|
sensor0_cameravdd-supply = <0x56>;
|
|
sensor0_cameravdd_vol = <0x2ab980>;
|
|
phandle = <0x1fd>;
|
|
};
|
|
|
|
sensor@5812010 {
|
|
reg = <0x00 0x5812010 0x00 0x10>;
|
|
device_type = "sensor1";
|
|
compatible = "allwinner,sunxi-sensor";
|
|
sensor1_mname = "ov13850_mipi";
|
|
sensor1_twi_cci_id = <0x03>;
|
|
sensor1_twi_addr = <0x20>;
|
|
sensor1_mclk_id = <0x02>;
|
|
sensor1_pos = "front";
|
|
sensor1_isp_used = <0x01>;
|
|
sensor1_fmt = <0x01>;
|
|
sensor1_stby_mode = <0x00>;
|
|
sensor1_vflip = <0x00>;
|
|
sensor1_hflip = <0x00>;
|
|
sensor1_iovdd-supply = <0xda>;
|
|
sensor1_iovdd_vol = <0x1b7740>;
|
|
sensor1_avdd-supply = <0xd9>;
|
|
sensor1_avdd_vol = <0x2ab980>;
|
|
sensor1_dvdd-supply = <0xdf>;
|
|
sensor1_dvdd_vol = <0x1b7740>;
|
|
sensor1_power_en;
|
|
sensor1_reset = <0x4b 0x04 0x09 0x01>;
|
|
sensor1_pwdn = <0x4b 0x04 0x08 0x00>;
|
|
sensor1_sm_vs;
|
|
flash_handle;
|
|
act_handle;
|
|
device_id = <0x01>;
|
|
status = "okay";
|
|
phandle = <0x1fe>;
|
|
};
|
|
|
|
sensor@5812020 {
|
|
reg = <0x00 0x5812020 0x00 0x10>;
|
|
device_type = "sensor2";
|
|
compatible = "allwinner,sunxi-sensor";
|
|
sensor2_mname = "imx386_mipi";
|
|
sensor2_twi_cci_id = <0x03>;
|
|
sensor2_twi_addr = <0x6c>;
|
|
sensor2_mclk_id = <0x01>;
|
|
sensor2_pos = "rear";
|
|
sensor2_isp_used = <0x00>;
|
|
sensor2_fmt = <0x00>;
|
|
sensor2_stby_mode = <0x00>;
|
|
sensor2_vflip = <0x00>;
|
|
sensor2_hflip = <0x00>;
|
|
sensor2_iovdd-supply;
|
|
sensor2_iovdd_vol;
|
|
sensor2_avdd-supply;
|
|
sensor2_avdd_vol;
|
|
sensor2_dvdd-supply;
|
|
sensor2_dvdd_vol;
|
|
sensor2_power_en;
|
|
sensor2_reset;
|
|
sensor2_pwdn;
|
|
sensor2_sm_vs;
|
|
flash_handle;
|
|
act_handle;
|
|
device_id = <0x02>;
|
|
status = "disabled";
|
|
phandle = <0x1ff>;
|
|
};
|
|
|
|
sensor@5812030 {
|
|
reg = <0x00 0x5812030 0x00 0x10>;
|
|
device_type = "sensor3";
|
|
compatible = "allwinner,sunxi-sensor";
|
|
sensor3_mname = "imx317_mipi";
|
|
sensor3_twi_cci_id = <0x03>;
|
|
sensor3_twi_addr = <0x6c>;
|
|
sensor3_mclk_id = <0x01>;
|
|
sensor3_pos = "rear";
|
|
sensor3_isp_used = <0x00>;
|
|
sensor3_fmt = <0x00>;
|
|
sensor3_stby_mode = <0x00>;
|
|
sensor3_vflip = <0x00>;
|
|
sensor3_hflip = <0x00>;
|
|
sensor3_iovdd-supply;
|
|
sensor3_iovdd_vol;
|
|
sensor3_avdd-supply;
|
|
sensor3_avdd_vol;
|
|
sensor3_dvdd-supply;
|
|
sensor3_dvdd_vol;
|
|
sensor3_power_en;
|
|
sensor3_reset;
|
|
sensor3_pwdn;
|
|
sensor3_sm_vs;
|
|
flash_handle;
|
|
act_handle;
|
|
device_id = <0x02>;
|
|
status = "disabled";
|
|
phandle = <0x200>;
|
|
};
|
|
|
|
sensor_list@5812040 {
|
|
reg = <0x00 0x5812040 0x00 0x10>;
|
|
device_type = "sensor_list0";
|
|
compatible = "allwinner,sunxi-sensor-list";
|
|
csi_sel = <0x00>;
|
|
sensor00_mname = "ov5675_mipi_b";
|
|
sensor00_twi_addr = <0x60>;
|
|
sensor00_type = <0x01>;
|
|
sensor00_hflip = <0x01>;
|
|
sensor00_vflip = <0x00>;
|
|
sensor00_act_used = <0x01>;
|
|
sensor00_act_name = "dw9714_act";
|
|
sensor00_act_twi_addr = <0x18>;
|
|
sensor01_mname = "gc05a2_mipi_b";
|
|
sensor01_twi_addr = <0x62>;
|
|
sensor01_type = <0x01>;
|
|
sensor01_hflip = <0x00>;
|
|
sensor01_vflip = <0x00>;
|
|
sensor01_act_used = <0x01>;
|
|
sensor01_act_name = "dw9714_act";
|
|
sensor01_act_twi_addr = <0x18>;
|
|
sensor02_mname = "gc5035_mipi_b";
|
|
sensor02_twi_addr = <0x64>;
|
|
sensor02_type = <0x01>;
|
|
sensor02_hflip = <0x00>;
|
|
sensor02_vflip = <0x00>;
|
|
sensor02_act_used = <0x01>;
|
|
sensor02_act_name = "dw9714_act";
|
|
sensor02_act_twi_addr = <0x18>;
|
|
device_id = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x201>;
|
|
};
|
|
|
|
sensor_list@5812050 {
|
|
reg = <0x00 0x5812050 0x00 0x10>;
|
|
device_type = "sensor_list1";
|
|
compatible = "allwinner,sunxi-sensor-list";
|
|
csi_sel = <0x00>;
|
|
sensor10_mname = "ov02a10_mipi_f";
|
|
sensor10_twi_addr = <0x70>;
|
|
sensor10_type = <0x01>;
|
|
sensor10_hflip = <0x01>;
|
|
sensor10_vflip = <0x00>;
|
|
sensor10_act_used = <0x00>;
|
|
sensor10_act_name = [00];
|
|
sensor10_act_twi_addr;
|
|
sensor11_mname = "gc02m1_mipi_f";
|
|
sensor11_twi_addr = <0x72>;
|
|
sensor11_type = <0x01>;
|
|
sensor11_hflip = <0x01>;
|
|
sensor11_vflip = <0x00>;
|
|
sensor11_act_used = <0x00>;
|
|
sensor11_act_name = [00];
|
|
sensor11_act_twi_addr;
|
|
sensor12_mname = "gc02m2_mipi_f";
|
|
sensor12_twi_addr = <0x74>;
|
|
sensor12_type = <0x01>;
|
|
sensor12_hflip = <0x00>;
|
|
sensor12_vflip = <0x00>;
|
|
sensor12_act_used = <0x00>;
|
|
sensor12_act_name = [00];
|
|
sensor12_act_twi_addr;
|
|
device_id = <0x01>;
|
|
status = "disabled";
|
|
phandle = <0x202>;
|
|
};
|
|
|
|
vinc@5830000 {
|
|
device_type = "vinc0";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5830000 0x00 0x1000>;
|
|
interrupts = <0x00 0x7a 0x04>;
|
|
vinc0_csi_sel = <0x02>;
|
|
vinc0_mipi_sel = <0x02>;
|
|
vinc0_isp_sel = <0x00>;
|
|
vinc0_isp_tx_ch = <0x00>;
|
|
vinc0_tdm_rx_sel = <0x00>;
|
|
vinc0_rear_sensor_sel = <0x00>;
|
|
vinc0_front_sensor_sel = <0x00>;
|
|
vinc0_sensor_list = <0x00>;
|
|
device_id = <0x00>;
|
|
work_mode = <0x00>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "okay";
|
|
phandle = <0x203>;
|
|
};
|
|
|
|
vinc@582fffc {
|
|
device_type = "vinc1";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x582fffc 0x00 0x1004>;
|
|
vinc1_csi_sel = <0x01>;
|
|
vinc1_mipi_sel = <0x02>;
|
|
vinc1_isp_sel = <0x01>;
|
|
vinc1_isp_tx_ch = <0x00>;
|
|
vinc1_tdm_rx_sel = <0x01>;
|
|
vinc1_rear_sensor_sel = <0x01>;
|
|
vinc1_front_sensor_sel = <0x01>;
|
|
vinc1_sensor_list = <0x00>;
|
|
device_id = <0x01>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x204>;
|
|
};
|
|
|
|
vinc@582fff8 {
|
|
device_type = "vinc2";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x582fff8 0x00 0x1008>;
|
|
vinc2_csi_sel = <0x02>;
|
|
vinc2_mipi_sel = <0xff>;
|
|
vinc2_isp_sel = <0x02>;
|
|
vinc2_isp_tx_ch = <0x02>;
|
|
vinc2_tdm_rx_sel = <0x02>;
|
|
vinc2_rear_sensor_sel = <0x00>;
|
|
vinc2_front_sensor_sel = <0x00>;
|
|
vinc2_sensor_list = <0x00>;
|
|
device_id = <0x02>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x205>;
|
|
};
|
|
|
|
vinc@582fff4 {
|
|
device_type = "vinc3";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x582fff4 0x00 0x100c>;
|
|
vinc3_csi_sel = <0x00>;
|
|
vinc3_mipi_sel = <0xff>;
|
|
vinc3_isp_sel = <0x00>;
|
|
vinc3_isp_tx_ch = <0x00>;
|
|
vinc3_tdm_rx_sel = <0x00>;
|
|
vinc3_rear_sensor_sel = <0x01>;
|
|
vinc3_front_sensor_sel = <0x01>;
|
|
vinc3_sensor_list = <0x00>;
|
|
device_id = <0x03>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x206>;
|
|
};
|
|
|
|
vinc@5831000 {
|
|
device_type = "vinc4";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5831000 0x00 0x1000>;
|
|
interrupts = <0x00 0x7b 0x04>;
|
|
vinc4_csi_sel = <0x00>;
|
|
vinc4_mipi_sel = <0x00>;
|
|
vinc4_isp_sel = <0x00>;
|
|
vinc4_isp_tx_ch = <0x00>;
|
|
vinc4_tdm_rx_sel = <0x00>;
|
|
vinc4_rear_sensor_sel = <0x00>;
|
|
vinc4_front_sensor_sel = <0x00>;
|
|
vinc4_sensor_list = <0x00>;
|
|
device_id = <0x04>;
|
|
work_mode = <0x00>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x207>;
|
|
};
|
|
|
|
vinc@5830ffc {
|
|
device_type = "vinc5";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5830ffc 0x00 0x1004>;
|
|
vinc5_csi_sel = <0x02>;
|
|
vinc5_mipi_sel = <0xff>;
|
|
vinc5_isp_sel = <0x01>;
|
|
vinc5_isp_tx_ch = <0x01>;
|
|
vinc5_tdm_rx_sel = <0x01>;
|
|
vinc5_rear_sensor_sel = <0x00>;
|
|
vinc5_front_sensor_sel = <0x00>;
|
|
vinc5_sensor_list = <0x00>;
|
|
device_id = <0x05>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x208>;
|
|
};
|
|
|
|
vinc@5830ff8 {
|
|
device_type = "vinc6";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5830ff8 0x00 0x1008>;
|
|
vinc6_csi_sel = <0x02>;
|
|
vinc6_mipi_sel = <0xff>;
|
|
vinc6_isp_sel = <0x00>;
|
|
vinc6_isp_tx_ch = <0x00>;
|
|
vinc6_tdm_rx_sel = <0x00>;
|
|
vinc6_rear_sensor_sel = <0x00>;
|
|
vinc6_front_sensor_sel = <0x00>;
|
|
vinc6_sensor_list = <0x00>;
|
|
device_id = <0x06>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x209>;
|
|
};
|
|
|
|
vinc@5830ff4 {
|
|
device_type = "vinc7";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5830ff4 0x00 0x100c>;
|
|
vinc7_csi_sel = <0x02>;
|
|
vinc7_mipi_sel = <0xff>;
|
|
vinc7_isp_sel = <0x00>;
|
|
vinc7_isp_tx_ch = <0x00>;
|
|
vinc7_tdm_rx_sel = <0x00>;
|
|
vinc7_rear_sensor_sel = <0x00>;
|
|
vinc7_front_sensor_sel = <0x00>;
|
|
vinc7_sensor_list = <0x00>;
|
|
device_id = <0x07>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x20a>;
|
|
};
|
|
|
|
vinc@5832000 {
|
|
device_type = "vinc8";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5832000 0x00 0x1000>;
|
|
interrupts = <0x00 0x7c 0x04>;
|
|
vinc8_csi_sel = <0x00>;
|
|
vinc8_mipi_sel = <0x00>;
|
|
vinc8_isp_sel = <0x00>;
|
|
vinc8_isp_tx_ch = <0x00>;
|
|
vinc8_tdm_rx_sel = <0x00>;
|
|
vinc8_rear_sensor_sel = <0x01>;
|
|
vinc8_front_sensor_sel = <0x01>;
|
|
vinc8_sensor_list = <0x00>;
|
|
device_id = <0x08>;
|
|
work_mode = <0x00>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "okay";
|
|
phandle = <0x20b>;
|
|
};
|
|
|
|
vinc@5831ffc {
|
|
device_type = "vinc9";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5831ffc 0x00 0x1004>;
|
|
vinc9_csi_sel = <0x02>;
|
|
vinc9_mipi_sel = <0xff>;
|
|
vinc9_isp_sel = <0x00>;
|
|
vinc9_isp_tx_ch = <0x00>;
|
|
vinc9_tdm_rx_sel = <0x00>;
|
|
vinc9_rear_sensor_sel = <0x00>;
|
|
vinc9_front_sensor_sel = <0x00>;
|
|
vinc9_sensor_list = <0x00>;
|
|
device_id = <0x09>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x20c>;
|
|
};
|
|
|
|
vinc@5831ff8 {
|
|
device_type = "vinc10";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5831ff8 0x00 0x1008>;
|
|
vinc10_csi_sel = <0x02>;
|
|
vinc10_mipi_sel = <0xff>;
|
|
vinc10_isp_sel = <0x00>;
|
|
vinc10_isp_tx_ch = <0x00>;
|
|
vinc10_tdm_rx_sel = <0x00>;
|
|
vinc10_rear_sensor_sel = <0x00>;
|
|
vinc10_front_sensor_sel = <0x00>;
|
|
vinc10_sensor_list = <0x00>;
|
|
device_id = <0x0a>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x20d>;
|
|
};
|
|
|
|
vinc@5831ff4 {
|
|
device_type = "vinc11";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5831ff4 0x00 0x100c>;
|
|
vinc11_csi_sel = <0x02>;
|
|
vinc11_mipi_sel = <0xff>;
|
|
vinc11_isp_sel = <0x00>;
|
|
vinc11_isp_tx_ch = <0x00>;
|
|
vinc11_tdm_rx_sel = <0x00>;
|
|
vinc11_rear_sensor_sel = <0x00>;
|
|
vinc11_front_sensor_sel = <0x00>;
|
|
vinc11_sensor_list = <0x00>;
|
|
device_id = <0x0b>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x20e>;
|
|
};
|
|
|
|
vinc@5833000 {
|
|
device_type = "vinc12";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5833000 0x00 0x1000>;
|
|
interrupts = <0x00 0x7d 0x04>;
|
|
vinc12_csi_sel = <0x02>;
|
|
vinc12_mipi_sel = <0x02>;
|
|
vinc12_isp_sel = <0x00>;
|
|
vinc12_isp_tx_ch = <0x00>;
|
|
vinc12_tdm_rx_sel = <0x00>;
|
|
vinc12_rear_sensor_sel = <0x01>;
|
|
vinc12_front_sensor_sel = <0x01>;
|
|
vinc12_sensor_list = <0x00>;
|
|
device_id = <0x0c>;
|
|
work_mode = <0x00>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x20f>;
|
|
};
|
|
|
|
vinc@5832ffc {
|
|
device_type = "vinc13";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5832ffc 0x00 0x1004>;
|
|
vinc13_csi_sel = <0x02>;
|
|
vinc13_mipi_sel = <0xff>;
|
|
vinc13_isp_sel = <0x00>;
|
|
vinc13_isp_tx_ch = <0x00>;
|
|
vinc13_tdm_rx_sel = <0x00>;
|
|
vinc13_rear_sensor_sel = <0x00>;
|
|
vinc13_front_sensor_sel = <0x00>;
|
|
vinc13_sensor_list = <0x00>;
|
|
device_id = <0x0d>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x210>;
|
|
};
|
|
|
|
vinc@5832ff8 {
|
|
device_type = "vinc14";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5832ff8 0x00 0x1008>;
|
|
vinc14_csi_sel = <0x02>;
|
|
vinc14_mipi_sel = <0xff>;
|
|
vinc14_isp_sel = <0x00>;
|
|
vinc14_isp_tx_ch = <0x00>;
|
|
vinc14_tdm_rx_sel = <0x00>;
|
|
vinc14_rear_sensor_sel = <0x00>;
|
|
vinc14_front_sensor_sel = <0x00>;
|
|
vinc14_sensor_list = <0x00>;
|
|
device_id = <0x0e>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x211>;
|
|
};
|
|
|
|
vinc@5832ff4 {
|
|
device_type = "vinc15";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5832ff4 0x00 0x100c>;
|
|
vinc15_csi_sel = <0x02>;
|
|
vinc15_mipi_sel = <0xff>;
|
|
vinc15_isp_sel = <0x00>;
|
|
vinc15_isp_tx_ch = <0x00>;
|
|
vinc15_tdm_rx_sel = <0x00>;
|
|
vinc15_rear_sensor_sel = <0x00>;
|
|
vinc15_front_sensor_sel = <0x00>;
|
|
vinc15_sensor_list = <0x00>;
|
|
device_id = <0x0f>;
|
|
work_mode = <0xff>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x212>;
|
|
};
|
|
|
|
vinc@5834000 {
|
|
device_type = "vinc16";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5834000 0x00 0x1000>;
|
|
interrupts = <0x00 0x91 0x04>;
|
|
vinc16_csi_sel = <0x02>;
|
|
vinc16_mipi_sel = <0xff>;
|
|
vinc16_isp_sel = <0x00>;
|
|
vinc16_isp_tx_ch = <0x00>;
|
|
vinc16_tdm_rx_sel = <0x00>;
|
|
vinc16_rear_sensor_sel = <0x00>;
|
|
vinc16_front_sensor_sel = <0x00>;
|
|
vinc16_sensor_list = <0x00>;
|
|
device_id = <0x10>;
|
|
work_mode = <0x00>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x213>;
|
|
};
|
|
|
|
vinc@5835000 {
|
|
device_type = "vinc17";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x00 0x5835000 0x00 0x1000>;
|
|
interrupts = <0x00 0x92 0x04>;
|
|
vinc17_csi_sel = <0x02>;
|
|
vinc17_mipi_sel = <0xff>;
|
|
vinc17_isp_sel = <0x00>;
|
|
vinc17_isp_tx_ch = <0x00>;
|
|
vinc17_tdm_rx_sel = <0x00>;
|
|
vinc17_rear_sensor_sel = <0x00>;
|
|
vinc17_front_sensor_sel = <0x00>;
|
|
vinc17_sensor_list = <0x00>;
|
|
device_id = <0x11>;
|
|
work_mode = <0x00>;
|
|
iommus = <0x1e 0x01 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x214>;
|
|
};
|
|
};
|
|
|
|
deinterlace@5400000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-deinterlace";
|
|
reg = <0x00 0x5400000 0x00 0x40000>;
|
|
interrupts = <0x00 0x58 0x04>;
|
|
iommus = <0x1e 0x06 0x01>;
|
|
power-domains = <0x1f 0x03>;
|
|
status = "okay";
|
|
clocks = <0x1a 0x36 0x1a 0x37 0x1a 0x1a>;
|
|
clock-names = "clk_di\0clk_bus_di\0clk_di_parent";
|
|
clock-frequency = <0x11e1a300>;
|
|
resets = <0x1a 0x03>;
|
|
reset-names = "rst_bus_di";
|
|
phandle = <0x215>;
|
|
};
|
|
|
|
gpu@1800000 {
|
|
device_type = "gpu";
|
|
compatible = "arm,mali-valhall";
|
|
reg = <0x00 0x1800000 0x00 0x10000>;
|
|
interrupts = <0x00 0x75 0x04 0x00 0x76 0x04 0x00 0x77 0x04>;
|
|
interrupt-names = "JOB\0MMU\0GPU";
|
|
clocks = <0x1a 0x3a 0x1a 0x3b 0x1a 0x18>;
|
|
clock-names = "clk_mali\0clk_bus\0clk_parent";
|
|
resets = <0x1a 0x05>;
|
|
operating-points-v2 = <0x10f>;
|
|
#cooling-cells = <0x02>;
|
|
gpu_idle = <0x01>;
|
|
dvfs_status = <0x01>;
|
|
mali-supply = <0x20>;
|
|
phandle = <0x16>;
|
|
|
|
ipa_dvfs {
|
|
compatible = "arm,mali-simple-power-model";
|
|
static-coefficient = <0x27c>;
|
|
dynamic-coefficient = <0x59a>;
|
|
ts = <0xcc77c0 0x34fa8 0xffffd508 0xc8>;
|
|
thermal-zone = "gpu_thermal_zone";
|
|
phandle = <0x216>;
|
|
};
|
|
};
|
|
|
|
gpu-opp-table {
|
|
compatible = "allwinner, mali-valhall-operating-points";
|
|
phandle = <0x10f>;
|
|
|
|
opp@150000000 {
|
|
opp-hz = <0x00 0x8f0d180>;
|
|
opp-microvolt = <0xdbba0>;
|
|
};
|
|
|
|
opp@200000000 {
|
|
opp-hz = <0x00 0xbebc200>;
|
|
opp-microvolt = <0xdbba0>;
|
|
};
|
|
|
|
opp@300000000 {
|
|
opp-hz = <0x00 0x11e1a300>;
|
|
opp-microvolt = <0xdbba0>;
|
|
};
|
|
|
|
opp@400000000 {
|
|
opp-hz = <0x00 0x17d78400>;
|
|
opp-microvolt = <0xdbba0>;
|
|
};
|
|
|
|
opp@600000000 {
|
|
opp-hz = <0x00 0x23c34600>;
|
|
opp-microvolt = <0xdbba0>;
|
|
};
|
|
|
|
opp@648000000 {
|
|
opp-hz = <0x00 0x269fb200>;
|
|
opp-microvolt = <0x00>;
|
|
opp-microvolt-vf0900 = <0xdbba0>;
|
|
};
|
|
|
|
opp@696000000 {
|
|
opp-hz = <0x00 0x297c1e00>;
|
|
opp-microvolt = <0x00>;
|
|
opp-microvolt-vf1920 = <0xdbba0>;
|
|
opp-microvolt-vf2920 = <0xdbba0>;
|
|
opp-microvolt-vf3920 = <0xdbba0>;
|
|
opp-microvolt-vf21920 = <0xdbba0>;
|
|
opp-microvolt-vf31920 = <0xdbba0>;
|
|
opp-microvolt-vf5920 = <0xdbba0>;
|
|
};
|
|
|
|
opp@744000000 {
|
|
opp-hz = <0x00 0x2c588a00>;
|
|
opp-microvolt = <0x00>;
|
|
opp-microvolt-vf4920 = <0xdbba0>;
|
|
};
|
|
|
|
opp@792000000 {
|
|
opp-hz = <0x00 0x2f34f600>;
|
|
opp-microvolt = <0x00>;
|
|
};
|
|
};
|
|
|
|
phy@4f00000 {
|
|
compatible = "allwinner,inno-combphy";
|
|
reg = <0x00 0x4f00000 0x00 0x80000 0x00 0x4f80000 0x00 0x80000>;
|
|
reg-names = "phy-ctl\0phy-clk";
|
|
power-domains = <0x1f 0x07>;
|
|
phy_refclk_sel = <0x00>;
|
|
clocks = <0x1a 0x8c 0x1a 0x09>;
|
|
clock-names = "phyclk_ref\0refclk_par";
|
|
resets = <0x1a 0x3b>;
|
|
reset-names = "phy_rst";
|
|
#phy-cells = <0x01>;
|
|
status = "okay";
|
|
clk-freq-100M;
|
|
phy_use_sel = <0x00>;
|
|
phandle = <0xf6>;
|
|
};
|
|
|
|
pcie@4800000 {
|
|
compatible = "allwinner,sunxi-pcie-v210-rc";
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
bus-range = <0x00 0xff>;
|
|
reg = <0x00 0x4800000 0x00 0x480000>;
|
|
reg-names = "dbi";
|
|
device_type = "pci";
|
|
ranges = <0x800 0x00 0x20000000 0x00 0x20000000 0x00 0x1000000 0x81000000 0x00 0x21000000 0x00 0x21000000 0x00 0x1000000 0x82000000 0x00 0x22000000 0x00 0x22000000 0x00 0xe000000>;
|
|
num-lanes = <0x01>;
|
|
phys = <0xf6 0x02>;
|
|
phy-names = "pcie-phy";
|
|
interrupts = <0x00 0x6b 0x04 0x00 0x6a 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04>;
|
|
interrupt-names = "msi\0sii\0edma-w0\0edma-w1\0edma-w2\0edma-w3\0edma-r0\0edma-r1\0edma-r2\0edma-r3";
|
|
#interrupt-cells = <0x01>;
|
|
num-edma = <0x04>;
|
|
max-link-speed = <0x02>;
|
|
num-ib-windows = <0x08>;
|
|
num-ob-windows = <0x08>;
|
|
linux,pci-domain = <0x00>;
|
|
power-domains = <0x1f 0x07>;
|
|
clocks = <0x22 0x1a 0x94>;
|
|
clock-names = "hosc\0pclk_aux";
|
|
status = "okay";
|
|
reset-gpios = <0x4b 0x07 0x0b 0x00>;
|
|
wake-gpios = <0x4b 0x07 0x0c 0x00>;
|
|
clk-freq-100M;
|
|
phandle = <0x217>;
|
|
};
|
|
|
|
codec@7110000 {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-codec";
|
|
reg = <0x00 0x7110000 0x00 0x348>;
|
|
resets = <0x78 0x06>;
|
|
clocks = <0x1a 0x02 0x1a 0xb5 0x78 0x04 0x78 0x15 0x1a 0x26 0x78 0x01 0x78 0x02 0x78 0x13 0x78 0x14>;
|
|
clock-names = "clk_pll_peri0_2x\0clk_dsp_src\0clk_dsp_core\0clk_bus_audio\0clk_pll_audio0_4x\0clk_pll_audio1_div2\0clk_pll_audio1_div5\0clk_audio_dac\0clk_audio_adc";
|
|
interrupts = <0x00 0xbe 0x04>;
|
|
status = "okay";
|
|
dac-vol = <0x3f>;
|
|
dacl-vol = <0xa0>;
|
|
dacr-vol = <0xa0>;
|
|
adc1-vol = <0xa0>;
|
|
adc2-vol = <0xa0>;
|
|
adc3-vol = <0xa0>;
|
|
lineout-gain = <0x1f>;
|
|
hpout-gain = <0x07>;
|
|
adc1-gain = <0x1f>;
|
|
adc2-gain = <0x1f>;
|
|
adc3-gain = <0x1f>;
|
|
avcc-external;
|
|
avcc-supply = <0xdc>;
|
|
avcc-vol = <0x1b7740>;
|
|
vdd-external;
|
|
vdd-supply = <0x65>;
|
|
vdd-vol = <0x325aa0>;
|
|
cpvin-external;
|
|
cpvin-supply = <0x4a>;
|
|
cpvin-vol = <0x1b7740>;
|
|
pa-pin-max = <0x01>;
|
|
pa-pin-0 = <0x4b 0x07 0x06 0x00>;
|
|
pa-pin-level-0 = <0x01>;
|
|
pa-pin-msleep-0 = <0x00>;
|
|
jack-det-level = <0x01>;
|
|
jack-det-threshold = <0x08>;
|
|
jack-det-debouce = <0x00>;
|
|
phandle = <0x111>;
|
|
};
|
|
|
|
codec_plat {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-plat-aaudio";
|
|
dac-txdata = <0x7110020>;
|
|
adc-txdata = <0x7110040>;
|
|
dmas = <0xcb 0x07 0xcb 0x07>;
|
|
dma-names = "tx\0rx";
|
|
playback-cma = <0x80>;
|
|
capture-cma = <0x80>;
|
|
tx-fifo-size = <0x80>;
|
|
rx-fifo-size = <0x80>;
|
|
status = "okay";
|
|
phandle = <0x110>;
|
|
};
|
|
|
|
codec_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "audiocodec";
|
|
soundcard-mach,pin-switches = "MIC1\0MIC2\0MIC3\0LINEOUTL\0LINEOUTR\0HPOUT\0SPK";
|
|
soundcard-mach,routing = "MIC1P_PIN\0MIC1\0MIC1N_PIN\0MIC1\0MIC2P_PIN\0MIC2\0MIC2N_PIN\0MIC2\0MIC3P_PIN\0MIC3\0MIC3N_PIN\0MIC3\0LINEOUTL\0LINEOUTLP_PIN\0LINEOUTL\0LINEOUTLN_PIN\0LINEOUTR\0LINEOUTRP_PIN\0LINEOUTR\0LINEOUTRN_PIN\0SPK\0LINEOUTLP_PIN\0SPK\0LINEOUTLN_PIN\0SPK\0LINEOUTRP_PIN\0SPK\0LINEOUTRN_PIN\0HPOUT\0HPOUTL_PIN\0HPOUT\0HPOUTR_PIN";
|
|
soundcard-mach,jack-support = <0x01>;
|
|
status = "okay";
|
|
phandle = <0x218>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x110>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
sound-dai = <0x111>;
|
|
soundcard-mach,pll-fs = <0x01>;
|
|
};
|
|
};
|
|
|
|
hdmi_codec {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-codec-hdmi";
|
|
status = "okay";
|
|
phandle = <0x11f>;
|
|
};
|
|
|
|
edp_codec {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-codec-edp";
|
|
status = "disabled";
|
|
phandle = <0x219>;
|
|
};
|
|
|
|
owa_plat@7116000 {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-plat-owa";
|
|
reg = <0x00 0x7116000 0x00 0x58>;
|
|
interrupts = <0x00 0xc4 0x04>;
|
|
resets = <0x78 0x04>;
|
|
clocks = <0x1a 0x02 0x1a 0xb5 0x78 0x04 0x78 0x10 0x1a 0x26 0x1a 0x08 0x78 0x01 0x78 0x02 0x78 0x0e 0x78 0x0f>;
|
|
clock-names = "clk_pll_peri0_2x\0clk_dsp_src\0clk_dsp_core\0clk_bus_owa\0clk_pll_audio0_4x\0clk_pll_peri0_300\0clk_pll_audio1_div2\0clk_pll_audio1_div5\0clk_owa_tx\0clk_owa_rx";
|
|
dmas = <0xcb 0x02 0xcb 0x02>;
|
|
dma-names = "tx\0rx";
|
|
playback-cma = <0x80>;
|
|
capture-cma = <0x80>;
|
|
tx-fifo-size = <0x80>;
|
|
rx-fifo-size = <0x80>;
|
|
status = "okay";
|
|
pinctrl-used;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x112>;
|
|
pinctrl-1 = <0x113>;
|
|
tx-hub-en;
|
|
phandle = <0x114>;
|
|
};
|
|
|
|
owa_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "sndowa";
|
|
status = "okay";
|
|
phandle = <0x21a>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x114>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
};
|
|
};
|
|
|
|
dmic_plat@7111000 {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-plat-dmic";
|
|
reg = <0x00 0x7111000 0x00 0x50>;
|
|
resets = <0x78 0x05>;
|
|
clocks = <0x1a 0x02 0x1a 0xb5 0x78 0x04 0x78 0x12 0x1a 0x26 0x78 0x01 0x78 0x02 0x78 0x11>;
|
|
clock-names = "clk_pll_peri0_2x\0clk_dsp_src\0clk_dsp_core\0clk_bus_dmic\0clk_pll_audio0_4x\0clk_pll_audio1_div2\0clk_pll_audio1_div5\0clk_dmic";
|
|
dmas = <0xcb 0x08>;
|
|
dma-names = "rx";
|
|
capture-cma = <0x80>;
|
|
rx-fifo-size = <0x80>;
|
|
status = "disabled";
|
|
rx-chmap = <0x76543210>;
|
|
data-vol = <0xb0>;
|
|
rxdelaytime = <0x00>;
|
|
rx-sync-en;
|
|
phandle = <0x115>;
|
|
};
|
|
|
|
dmic_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "snddmic";
|
|
soundcard-mach,capture-only;
|
|
status = "disabled";
|
|
phandle = <0x21b>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x115>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
};
|
|
};
|
|
|
|
i2s0_plat@7112000 {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-plat-i2s";
|
|
reg = <0x00 0x7112000 0x00 0xa0>;
|
|
resets = <0x78 0x03>;
|
|
clocks = <0x1a 0x02 0x1a 0xb5 0x78 0x04 0x78 0x0a 0x1a 0x26 0x78 0x01 0x78 0x02 0x78 0x05>;
|
|
clock-names = "clk_pll_peri0_2x\0clk_dsp_src\0clk_dsp_core\0clk_bus_i2s\0clk_pll_audio0_4x\0clk_pll_audio1_div2\0clk_pll_audio1_div5\0clk_i2s";
|
|
dmas = <0xcb 0x03 0xcb 0x03>;
|
|
dma-names = "tx\0rx";
|
|
playback-cma = <0x80>;
|
|
capture-cma = <0x80>;
|
|
tx-fifo-size = <0x80>;
|
|
rx-fifo-size = <0x80>;
|
|
status = "disabled";
|
|
phandle = <0x116>;
|
|
};
|
|
|
|
i2s0_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "sndi2s0";
|
|
soundcard-mach,format = "i2s";
|
|
soundcard-mach,slot-num = <0x02>;
|
|
soundcard-mach,slot-width = <0x20>;
|
|
status = "disabled";
|
|
phandle = <0x21c>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x116>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
};
|
|
};
|
|
|
|
i2s1_plat@7113000 {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-plat-i2s";
|
|
reg = <0x00 0x7113000 0x00 0xa0>;
|
|
resets = <0x78 0x02>;
|
|
clocks = <0x1a 0x02 0x1a 0xb5 0x78 0x04 0x78 0x0b 0x1a 0x26 0x78 0x01 0x78 0x02 0x78 0x06>;
|
|
clock-names = "clk_pll_peri0_2x\0clk_dsp_src\0clk_dsp_core\0clk_bus_i2s\0clk_pll_audio0_4x\0clk_pll_audio1_div2\0clk_pll_audio1_div5\0clk_i2s";
|
|
dmas = <0xcb 0x04 0xcb 0x04>;
|
|
dma-names = "tx\0rx";
|
|
playback-cma = <0x80>;
|
|
capture-cma = <0x80>;
|
|
tx-fifo-size = <0x80>;
|
|
rx-fifo-size = <0x80>;
|
|
status = "okay";
|
|
tdm-num = <0x01>;
|
|
tx-pin = <0x00>;
|
|
tx-pin0-map0 = <0x76543210>;
|
|
tx-pin0-map1 = <0xfedcba98>;
|
|
rx-pin = <0x00>;
|
|
pinctrl-used;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x117 0x118 0x119>;
|
|
pinctrl-1 = <0x11a>;
|
|
tx-hub-en;
|
|
rx-sync-en;
|
|
phandle = <0x11c>;
|
|
};
|
|
|
|
i2s1_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "sndi2s1";
|
|
soundcard-mach,format = "dsp_a";
|
|
soundcard-mach,slot-num = <0x02>;
|
|
soundcard-mach,slot-width = <0x20>;
|
|
status = "okay";
|
|
soundcard-mach,frame-master = <0x11b>;
|
|
soundcard-mach,bitclock-master = <0x11b>;
|
|
soundcard-mach,bitclock-inversion;
|
|
phandle = <0x21d>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x11c>;
|
|
soundcard-mach,pll-fs = <0x01>;
|
|
soundcard-mach,mclk-fs = <0x00>;
|
|
phandle = <0x11b>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
phandle = <0x21e>;
|
|
};
|
|
};
|
|
|
|
i2s2_plat@7114000 {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-plat-i2s";
|
|
reg = <0x00 0x7114000 0x00 0xa0>;
|
|
resets = <0x78 0x01>;
|
|
clocks = <0x1a 0x02 0x1a 0xb5 0x78 0x04 0x78 0x0c 0x1a 0x26 0x78 0x01 0x78 0x02 0x78 0x07>;
|
|
clock-names = "clk_pll_peri0_2x\0clk_dsp_src\0clk_dsp_core\0clk_bus_i2s\0clk_pll_audio0_4x\0clk_pll_audio1_div2\0clk_pll_audio1_div5\0clk_i2s";
|
|
dmas = <0xcb 0x05 0xcb 0x05>;
|
|
dma-names = "tx\0rx";
|
|
playback-cma = <0x80>;
|
|
capture-cma = <0x80>;
|
|
tx-fifo-size = <0x80>;
|
|
rx-fifo-size = <0x80>;
|
|
status = "okay";
|
|
tdm-num = <0x02>;
|
|
tx-pin = <0x00 0x01 0x02 0x03>;
|
|
tx-pin0-map0 = <0x76543210>;
|
|
tx-pin0-map1 = <0xfedcba98>;
|
|
tx-pin1-map0 = <0x76543210>;
|
|
tx-pin1-map1 = <0xfedcba98>;
|
|
tx-pin2-map0 = <0x76543210>;
|
|
tx-pin2-map1 = <0xfedcba98>;
|
|
tx-pin3-map0 = <0x76543210>;
|
|
tx-pin3-map1 = <0xfedcba98>;
|
|
rx-pin = <0x00>;
|
|
tx-hub-en;
|
|
rx-sync-en;
|
|
dai-type = "hdmi";
|
|
phandle = <0x11e>;
|
|
};
|
|
|
|
i2s2_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "sndhdmi";
|
|
soundcard-mach,format = "i2s";
|
|
soundcard-mach,slot-num = <0x02>;
|
|
soundcard-mach,slot-width = <0x20>;
|
|
status = "okay";
|
|
soundcard-mach,frame-master = <0x11d>;
|
|
soundcard-mach,bitclock-master = <0x11d>;
|
|
soundcard-mach,playback-only;
|
|
phandle = <0x21f>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x11e>;
|
|
soundcard-mach,pll-fs = <0x01>;
|
|
soundcard-mach,mclk-fs = <0x00>;
|
|
phandle = <0x11d>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
sound-dai = <0x11f>;
|
|
phandle = <0x220>;
|
|
};
|
|
};
|
|
|
|
i2s3_plat@7115000 {
|
|
#sound-dai-cells = <0x00>;
|
|
compatible = "allwinner,sunxi-snd-plat-i2s";
|
|
reg = <0x00 0x7115000 0x00 0xa0>;
|
|
resets = <0x78 0x00>;
|
|
clocks = <0x1a 0x02 0x1a 0xb5 0x78 0x04 0x78 0x0d 0x1a 0x26 0x1a 0x08 0x78 0x01 0x78 0x02 0x78 0x09 0x78 0x08>;
|
|
clock-names = "clk_pll_peri0_2x\0clk_dsp_src\0clk_dsp_core\0clk_bus_i2s\0clk_pll_audio0_4x\0clk_pll_peri0_300\0clk_pll_audio1_div2\0clk_pll_audio1_div5\0clk_i2s_asrc\0clk_i2s";
|
|
dmas = <0xcb 0x06 0xcb 0x06>;
|
|
dma-names = "tx\0rx";
|
|
playback-cma = <0x80>;
|
|
capture-cma = <0x80>;
|
|
tx-fifo-size = <0x80>;
|
|
rx-fifo-size = <0x80>;
|
|
status = "disabled";
|
|
tdm-num = <0x03>;
|
|
tx-pin = <0x00>;
|
|
tx-pin0-map0 = <0x76543210>;
|
|
tx-pin0-map1 = <0xfedcba98>;
|
|
rx-pin = <0x00>;
|
|
tx-hub-en;
|
|
rx-sync-en;
|
|
phandle = <0x121>;
|
|
};
|
|
|
|
i2s3_mach {
|
|
compatible = "allwinner,sunxi-snd-mach";
|
|
soundcard-mach,name = "sndi2s3";
|
|
soundcard-mach,format = "i2s";
|
|
soundcard-mach,slot-num = <0x02>;
|
|
soundcard-mach,slot-width = <0x20>;
|
|
status = "disabled";
|
|
soundcard-mach,frame-master = <0x120>;
|
|
soundcard-mach,bitclock-master = <0x120>;
|
|
phandle = <0x221>;
|
|
|
|
soundcard-mach,cpu {
|
|
sound-dai = <0x121>;
|
|
soundcard-mach,pll-fs = <0x01>;
|
|
soundcard-mach,mclk-fs = <0x00>;
|
|
phandle = <0x120>;
|
|
};
|
|
|
|
soundcard-mach,codec {
|
|
phandle = <0x222>;
|
|
};
|
|
};
|
|
|
|
rfkill {
|
|
compatible = "allwinner,sunxi-rfkill";
|
|
status = "okay";
|
|
chip_en;
|
|
power_en;
|
|
pinctrl-0;
|
|
pinctrl-names;
|
|
phandle = <0x223>;
|
|
|
|
wlan {
|
|
compatible = "allwinner,sunxi-wlan";
|
|
clocks = <0x23 0x08>;
|
|
clock-names = "osc32k-out";
|
|
wlan_power = "axp2202-aldo3\0axp2202-bldo1\0axp2202-bldo2";
|
|
wlan_power_vol = <0x325aa0 0x1b7740 0x1b7740>;
|
|
wlan_busnum = <0x01>;
|
|
wlan_regon = <0x62 0x01 0x01 0x00>;
|
|
wlan_hostwake = <0x62 0x01 0x00 0x00>;
|
|
wakeup-source;
|
|
};
|
|
|
|
bt {
|
|
compatible = "allwinner,sunxi-bt";
|
|
clocks = <0x23 0x08>;
|
|
clock-names = "osc32k-out";
|
|
bt_power = "axp2202-aldo3\0axp2202-bldo1\0axp2202-bldo2";
|
|
bt_power_vol = <0x325aa0 0x1b7740 0x1b7740>;
|
|
bt_rst_n = <0x62 0x01 0x02 0x01>;
|
|
};
|
|
};
|
|
|
|
addr_mgt {
|
|
compatible = "allwinner,sunxi-addr_mgt";
|
|
status = "okay";
|
|
type_addr_wifi = <0x00>;
|
|
type_addr_bt = <0x00>;
|
|
type_addr_eth = <0x00>;
|
|
phandle = <0x224>;
|
|
};
|
|
|
|
btlpm {
|
|
compatible = "allwinner,sunxi-btlpm";
|
|
status = "okay";
|
|
uart_index = <0x01>;
|
|
bt_wake = <0x62 0x01 0x03 0x00>;
|
|
bt_hostwake = <0x62 0x01 0x04 0x00>;
|
|
wakeup-source;
|
|
phandle = <0x225>;
|
|
};
|
|
|
|
mdio0@4500048 {
|
|
compatible = "allwinner,sunxi-mdio";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00 0x4500048 0x00 0x08>;
|
|
status = "disabled";
|
|
phandle = <0x226>;
|
|
|
|
ethernet-phy@1 {
|
|
reg = <0x01>;
|
|
max-speed = <0x3e8>;
|
|
reset-gpios = <0x4b 0x07 0x13 0x01>;
|
|
reset-assert-us = <0x2710>;
|
|
reset-deassert-us = <0x249f0>;
|
|
phandle = <0x122>;
|
|
};
|
|
};
|
|
|
|
gmac0@4500000 {
|
|
compatible = "allwinner,sunxi-gmac";
|
|
reg = <0x00 0x4500000 0x00 0x10000 0x00 0x3000030 0x00 0x04>;
|
|
interrupts = <0x00 0x2e 0x04>;
|
|
interrupt-names = "gmacirq";
|
|
clocks = <0x1a 0x7e 0x1a 0x7b>;
|
|
clock-names = "gmac\0phy25m";
|
|
resets = <0x1a 0x2a>;
|
|
phy-handle = <0x122>;
|
|
status = "disabled";
|
|
phandle = <0x227>;
|
|
};
|
|
|
|
ethernet@4510000 {
|
|
compatible = "allwinner,sunxi-gmac-200\0snps,dwmac-4.20a";
|
|
reg = <0x00 0x4510000 0x00 0x10000 0x00 0x3000034 0x00 0x04>;
|
|
interrupts = <0x00 0x2f 0x04>;
|
|
interrupt-names = "macirq";
|
|
clocks = <0x1a 0x7d 0x1a 0x52 0x1a 0x7c>;
|
|
clock-names = "stmmaceth\0pclk\0phy25m";
|
|
resets = <0x1a 0x29>;
|
|
reset-names = "stmmaceth";
|
|
phy-handle = <0x123>;
|
|
power-domains = <0x1f 0x04>;
|
|
status = "okay";
|
|
snps,fixed-burst;
|
|
snps,axi-config = <0x124>;
|
|
snps,mtl-rx-config = <0x125>;
|
|
snps,mtl-tx-config = <0x126>;
|
|
phy-mode = "rgmii";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x127>;
|
|
pinctrl-1 = <0x128>;
|
|
aw,soc-phy25m;
|
|
tx-delay = <0x03>;
|
|
rx-delay = <0x04>;
|
|
dwmac3v3-supply = <0x65>;
|
|
phandle = <0x228>;
|
|
|
|
stmmac-axi-config {
|
|
snps,wr_osr_lmt = <0x0f>;
|
|
snps,rd_osr_lmt = <0x0f>;
|
|
snps,blen = <0x100 0x80 0x40 0x20 0x10 0x08 0x04>;
|
|
phandle = <0x124>;
|
|
};
|
|
|
|
rx-queues-config {
|
|
snps,rx-queues-to-use = <0x01>;
|
|
phandle = <0x125>;
|
|
|
|
queue0 {
|
|
};
|
|
};
|
|
|
|
tx_queues-config {
|
|
snps,tx-queues-to-use = <0x01>;
|
|
phandle = <0x126>;
|
|
|
|
queue0 {
|
|
};
|
|
};
|
|
|
|
mdio1@1 {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x229>;
|
|
|
|
ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <0x01>;
|
|
max-speed = <0x3e8>;
|
|
reset-gpios = <0x4b 0x08 0x0f 0x01>;
|
|
reset-assert-us = <0x2710>;
|
|
reset-deassert-us = <0x249f0>;
|
|
phandle = <0x123>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ioserial@0 {
|
|
compatible = "allwinner,ioserial-100";
|
|
tx-gpios = <0x4b 0x01 0x0b 0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sid@3006000 {
|
|
compatible = "allwinner,sun55iw3p1-sid\0allwinner,sunxi-sid";
|
|
reg = <0x00 0x3006000 0x00 0x1000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
non-secure-maxoffset = <0x80>;
|
|
non-secure-maxlen = <0x20>;
|
|
|
|
secure_status {
|
|
reg = <0x00 0x00>;
|
|
offset = <0xa0>;
|
|
size = <0x04>;
|
|
};
|
|
|
|
chipid {
|
|
reg = <0x00 0x00>;
|
|
offset = <0x200>;
|
|
size = <0x10>;
|
|
};
|
|
|
|
rotpk {
|
|
reg = <0x00 0x00>;
|
|
offset = <0x140>;
|
|
size = <0x20>;
|
|
};
|
|
};
|
|
|
|
sram_ctrl@3000000 {
|
|
compatible = "allwinner,sram_ctrl";
|
|
reg = <0x00 0x3000000 0x00 0x184>;
|
|
phandle = <0x22a>;
|
|
|
|
soc_ver {
|
|
offset = <0x24>;
|
|
mask = <0x07>;
|
|
shift = <0x00>;
|
|
ver_a = <0x00>;
|
|
ver_b = <0x01>;
|
|
ver_c = <0x02>;
|
|
};
|
|
|
|
soc_id {
|
|
offset = <0x200>;
|
|
mask = <0x01>;
|
|
shift = <0x16>;
|
|
};
|
|
|
|
soc_bin {
|
|
offset = <0x00>;
|
|
mask = <0x3ff>;
|
|
shift = <0x00>;
|
|
};
|
|
};
|
|
|
|
auto_print@54321 {
|
|
reg = <0x00 0x54321 0x00 0x00>;
|
|
device_type = "auto_print";
|
|
status = "okay";
|
|
};
|
|
|
|
hall_para {
|
|
hall_name = "MH248";
|
|
status = "okay";
|
|
hall_int_port = <0x62 0x00 0x09 0x01>;
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory {
|
|
reg = <0x00 0x40000000 0x01 0x00>;
|
|
device_type = "memory";
|
|
};
|
|
|
|
gpio-leds {
|
|
compatible = "gpio-leds";
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
phandle = <0x22b>;
|
|
|
|
status_led@0 {
|
|
gpios = <0x4b 0x03 0x14 0x00>;
|
|
label = "status_led";
|
|
linux,default-trigger = "heartbeat";
|
|
linux,default-trigger-delay-ms = <0x00>;
|
|
};
|
|
};
|
|
|
|
ap6256_wifi {
|
|
compatible = "android,bcmdhd_wlan";
|
|
gpio_wl_reg_on = <0x62 0x01 0x01 0x00>;
|
|
gpio_wl_host_wake = <0x62 0x01 0x00 0x00>;
|
|
phandle = <0x22c>;
|
|
};
|
|
|
|
exxt-vbus {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "exxxxt-vbus";
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
gpio = <0x62 0x00 0x08 0x00>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
enable-active-high;
|
|
phandle = <0x22d>;
|
|
};
|
|
|
|
usb0-vbus {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "usb0-vbus";
|
|
regulator-min-microvolt = <0x4c4b40>;
|
|
regulator-max-microvolt = <0x4c4b40>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
gpio = <0x62 0x00 0x04 0x00>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
enable-active-high;
|
|
phandle = <0x22e>;
|
|
};
|
|
|
|
usb1-vbus {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "usb1-vbus";
|
|
regulator-min-microvolt = <0x4c4b40>;
|
|
regulator-max-microvolt = <0x4c4b40>;
|
|
regulator-enable-ramp-delay = <0x3e8>;
|
|
gpio = <0x62 0x00 0x0c 0x00>;
|
|
enable-active-high;
|
|
phandle = <0xf4>;
|
|
};
|
|
|
|
standby_param {
|
|
vdd-cpu = <0x01>;
|
|
vdd-cpub = <0x01>;
|
|
vdd-ndr = <0x04>;
|
|
vdd-sys = <0x02>;
|
|
vcc-pll = <0x80>;
|
|
vcc-io = <0x4000>;
|
|
osc24m-on = <0x00>;
|
|
phandle = <0x22f>;
|
|
};
|
|
|
|
arisc_config {
|
|
phandle = <0x230>;
|
|
|
|
s_uart_config {
|
|
pins = "PL2\0PL3";
|
|
function = <0x02 0x02>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
edp_panel {
|
|
compatible = "edp-general-panel";
|
|
status = "disabled";
|
|
power0-supply = <0xd7>;
|
|
enable0-gpios = <0x4b 0x03 0x15 0x00>;
|
|
backlight = <0x129>;
|
|
phandle = <0x57>;
|
|
|
|
panel-timing {
|
|
clock-frequency = <0x7735940>;
|
|
hactive = <0x780>;
|
|
hback-porch = <0xb4>;
|
|
hfront-porch = <0x78>;
|
|
hsync-len = <0x20>;
|
|
vactive = <0x438>;
|
|
vback-porch = <0x0a>;
|
|
vfront-porch = <0x0a>;
|
|
vsync-len = <0x14>;
|
|
hsync-active = <0x00>;
|
|
vsync-active = <0x00>;
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
phandle = <0x231>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x12a>;
|
|
phandle = <0x59>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
edp-panel-backlight {
|
|
compatible = "pwm-backlight";
|
|
brightness-levels = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
|
|
default-brightness-level = <0xc8>;
|
|
pwms = <0x12b 0x00 0xc350 0x00>;
|
|
phandle = <0x129>;
|
|
};
|
|
|
|
backlight0 {
|
|
compatible = "pwm-backlight";
|
|
brightness-levels = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
|
|
default-brightness-level = <0xc8>;
|
|
pwms = <0x12b 0x03 0xc350 0x00>;
|
|
phandle = <0x4c>;
|
|
};
|
|
|
|
axp2202-parameter {
|
|
select = "battery-model";
|
|
phandle = <0xd5>;
|
|
|
|
battery-model {
|
|
parameter = <0x1f54000 0x1b1e280f 0xc1e3202 0x14050a04 0x74fbc80d 0x4310ccfb 0x4601ea14 0x1006cc06 0x9d0b630f 0xf40f940a 0x4f0ef40e 0xeb04dd04 0xd109c70e 0xb90eb609 0xae0e970e 0x97048604 0x7309690e 0x600e1e08 0x21582822 0x18060d01 0xc5987e66 0x4e44381a 0x120af600 0xf600f6 0xfb0000 0xfb0000fb 0xf600 0xf600f6 0xfb0000 0xfb0000fb 0xf600 0xf600f6>;
|
|
};
|
|
};
|
|
|
|
__symbols__ {
|
|
reg_vdd_sys = "/vdd-sys";
|
|
cpu0 = "/cpus/cpu@0";
|
|
cpu1 = "/cpus/cpu@100";
|
|
cpu2 = "/cpus/cpu@200";
|
|
cpu3 = "/cpus/cpu@300";
|
|
cpu4 = "/cpus/cpu@400";
|
|
cpu5 = "/cpus/cpu@500";
|
|
cpu6 = "/cpus/cpu@600";
|
|
cpu7 = "/cpus/cpu@700";
|
|
CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0";
|
|
CLUSTER_SLEEP_0 = "/cpus/idle-states/cluster-sleep-0";
|
|
vf_mapping_table = "/vf_mapping_table";
|
|
gpu_vf_mapping_table = "/gpu_vf_mapping_table";
|
|
npu_vf_mapping_table = "/npu_vf_mapping_table";
|
|
cluster0_opp_table = "/cluster0-opp-table";
|
|
cluster1_opp_table = "/cluster1-opp-table";
|
|
dsufreq = "/dsufreq@0";
|
|
dsu_opp_table = "/dsu-opp-table";
|
|
cpul_thermal_zone = "/thermal-zones/cpul_thermal_zone";
|
|
cpul_trips = "/thermal-zones/cpul_thermal_zone/trips";
|
|
cpul_threshold = "/thermal-zones/cpul_thermal_zone/trips/trip-point@0";
|
|
cpul_target = "/thermal-zones/cpul_thermal_zone/trips/trip-point@1";
|
|
cpul_crit = "/thermal-zones/cpul_thermal_zone/trips/cpu_crit@0";
|
|
cpub_thermal_zone = "/thermal-zones/cpub_thermal_zone";
|
|
cpub_trips = "/thermal-zones/cpub_thermal_zone/trips";
|
|
cpub_threshold = "/thermal-zones/cpub_thermal_zone/trips/trip-point@0";
|
|
cpub_target = "/thermal-zones/cpub_thermal_zone/trips/trip-point@1";
|
|
cpub_crit = "/thermal-zones/cpub_thermal_zone/trips/cpu_crit@0";
|
|
gpu_thermal_zone = "/thermal-zones/gpu_thermal_zone";
|
|
gpu_trips = "/thermal-zones/gpu_thermal_zone/trips";
|
|
gpu_threshold = "/thermal-zones/gpu_thermal_zone/trips/trip-point@0";
|
|
gpu_target = "/thermal-zones/gpu_thermal_zone/trips/trip-point@1";
|
|
gpu_crit = "/thermal-zones/gpu_thermal_zone/trips/gpu_crit@0";
|
|
dcxo24M = "/dcxo24M_clk";
|
|
rc_16m = "/rc16m_clk";
|
|
ext_32k = "/ext32k_clk";
|
|
gic = "/interrupt-controller@3400000";
|
|
wakeupgen = "/interrupt-controller@0";
|
|
power = "/power-management@7001400";
|
|
pd = "/power-management@7001400/power-controller";
|
|
pck = "/pck-600@7060000";
|
|
pd1 = "/pck-600@7060000/power-controller";
|
|
nmi_intc = "/intc-nmi@7010320";
|
|
mmu_aw = "/iommu@2010000";
|
|
dram = "/dram";
|
|
ddr_clk = "/clk_ddr";
|
|
dram_opp_table = "/opp_table";
|
|
sunxi_dmcfreq = "/dmcfreq@3120000";
|
|
soc = "/soc@3000000";
|
|
ve = "/soc@3000000/ve@1c0e000";
|
|
ve1 = "/soc@3000000/ve1@1c0e000";
|
|
pd_ve_test = "/soc@3000000/pd-ve-test@0";
|
|
pd_vi_test = "/soc@3000000/pd-vi-test@0";
|
|
pd_vo0_test = "/soc@3000000/pd-vo0-test@0";
|
|
pd_vo1_test = "/soc@3000000/pd-vo1-test@0";
|
|
pd_de_test = "/soc@3000000/pd-de-test@0";
|
|
pd_nand_test = "/soc@3000000/pd-nand-test@0";
|
|
pd_pcie_test = "/soc@3000000/pd-pcie-test@0";
|
|
pd_dsp_test = "/soc@3000000/pd-dsp-test@0";
|
|
pd_npu_test = "/soc@3000000/pd-npu-test@0";
|
|
pd_sram_test = "/soc@3000000/pd-sram-test@0";
|
|
pd_riscv_test = "/soc@3000000/pd-riscv-test@0";
|
|
test_ccu = "/soc@3000000/test_ccu@3000090";
|
|
rtc_ccu = "/soc@3000000/rtc_ccu@7090000";
|
|
cpupll_ccu = "/soc@3000000/clock@8817000";
|
|
ccu = "/soc@3000000/ccu@2001000";
|
|
r_ccu = "/soc@3000000/r_ccu@7010000";
|
|
mcu_ccu = "/soc@3000000/mcu_ccu@7102000";
|
|
sunxi_drm = "/soc@3000000/sunxi-drm";
|
|
de = "/soc@3000000/de@5000000";
|
|
disp0 = "/soc@3000000/de@5000000/ports/port@0";
|
|
disp0_out_tcon0 = "/soc@3000000/de@5000000/ports/port@0/endpoint@0";
|
|
disp0_out_tcon1 = "/soc@3000000/de@5000000/ports/port@0/endpoint@1";
|
|
disp0_out_tcon2 = "/soc@3000000/de@5000000/ports/port@0/endpoint@2";
|
|
disp0_out_tcon3 = "/soc@3000000/de@5000000/ports/port@0/endpoint@3";
|
|
disp0_out_tcon4 = "/soc@3000000/de@5000000/ports/port@0/endpoint@4";
|
|
disp1 = "/soc@3000000/de@5000000/ports/port@1";
|
|
disp1_out_tcon0 = "/soc@3000000/de@5000000/ports/port@1/endpoint@0";
|
|
disp1_out_tcon1 = "/soc@3000000/de@5000000/ports/port@1/endpoint@1";
|
|
disp1_out_tcon2 = "/soc@3000000/de@5000000/ports/port@1/endpoint@2";
|
|
disp1_out_tcon3 = "/soc@3000000/de@5000000/ports/port@1/endpoint@3";
|
|
disp1_out_tcon4 = "/soc@3000000/de@5000000/ports/port@1/endpoint@4";
|
|
vo0 = "/soc@3000000/vo0@5500000";
|
|
vo1 = "/soc@3000000/vo1@5730000";
|
|
dlcd0 = "/soc@3000000/tcon0@5501000";
|
|
tcon0_in = "/soc@3000000/tcon0@5501000/ports/port@0";
|
|
tcon0_in_disp0 = "/soc@3000000/tcon0@5501000/ports/port@0/endpoint@0";
|
|
tcon0_in_disp1 = "/soc@3000000/tcon0@5501000/ports/port@0/endpoint@1";
|
|
tcon0_out = "/soc@3000000/tcon0@5501000/ports/port@1";
|
|
tcon0_out_lvds0 = "/soc@3000000/tcon0@5501000/ports/port@1/endpoint@0";
|
|
tcon0_out_dsi0 = "/soc@3000000/tcon0@5501000/ports/port@1/endpoint@1";
|
|
tcon0_out_dsi1 = "/soc@3000000/tcon0@5501000/ports/port@1/endpoint@2";
|
|
tcon0_out_rgb0 = "/soc@3000000/tcon0@5501000/ports/port@1/endpoint@3";
|
|
dlcd1 = "/soc@3000000/tcon1@5502000";
|
|
tcon1_in = "/soc@3000000/tcon1@5502000/ports/port@0";
|
|
tcon1_in_disp0 = "/soc@3000000/tcon1@5502000/ports/port@0/endpoint@0";
|
|
tcon1_in_disp1 = "/soc@3000000/tcon1@5502000/ports/port@0/endpoint@1";
|
|
tcon1_out = "/soc@3000000/tcon1@5502000/ports/port@1";
|
|
tcon1_out_dsi1 = "/soc@3000000/tcon1@5502000/ports/port@1/endpoint@0";
|
|
dlcd2 = "/soc@3000000/tcon4@5731000";
|
|
tcon4_in = "/soc@3000000/tcon4@5731000/ports/port@0";
|
|
tcon4_in_disp0 = "/soc@3000000/tcon4@5731000/ports/port@0/endpoint@0";
|
|
tcon4_in_disp1 = "/soc@3000000/tcon4@5731000/ports/port@0/endpoint@1";
|
|
tcon4_out = "/soc@3000000/tcon4@5731000/ports/port@1";
|
|
tcon4_out_lvds1 = "/soc@3000000/tcon4@5731000/ports/port@1/endpoint@0";
|
|
tcon4_out_rgb1 = "/soc@3000000/tcon4@5731000/ports/port@1/endpoint@1";
|
|
lvds0 = "/soc@3000000/lvds0@0001000";
|
|
lvds0_in = "/soc@3000000/lvds0@0001000/ports/port@0";
|
|
lvds0_in_tcon0 = "/soc@3000000/lvds0@0001000/ports/port@0/endpoint@0";
|
|
lvds1 = "/soc@3000000/lvds1@0001000";
|
|
lvds1_in = "/soc@3000000/lvds1@0001000/ports/port@0";
|
|
lvds1_in_tcon4 = "/soc@3000000/lvds1@0001000/ports/port@0/endpoint@0";
|
|
rgb0 = "/soc@3000000/rgb0@0001000";
|
|
rgb0_in = "/soc@3000000/rgb0@0001000/ports/port@0";
|
|
rgb0_in_tcon0 = "/soc@3000000/rgb0@0001000/ports/port@0/endpoint@0";
|
|
rgb1 = "/soc@3000000/rgb1@0001000";
|
|
rgb1_in = "/soc@3000000/rgb1@0001000/ports/port@0";
|
|
rgb1_in_tcon4 = "/soc@3000000/rgb1@0001000/ports/port@0/endpoint@0";
|
|
dsi0combophy = "/soc@3000000/phy@5507000";
|
|
dsi0 = "/soc@3000000/dsi0@5506000";
|
|
dsi0_in = "/soc@3000000/dsi0@5506000/ports/port@0";
|
|
dsi0_in_tcon0 = "/soc@3000000/dsi0@5506000/ports/port@0/endpoint@0";
|
|
dsi1combophy = "/soc@3000000/phy@5509000";
|
|
dsi1 = "/soc@3000000/dsi1@5508000";
|
|
dsi1_in = "/soc@3000000/dsi1@5508000/ports/port@0";
|
|
dsi1_in_tcon1 = "/soc@3000000/dsi1@5508000/ports/port@0/endpoint@0";
|
|
dsi1_in_tcon0 = "/soc@3000000/dsi1@5508000/ports/port@0/endpoint@1";
|
|
panel = "/soc@3000000/dsi1@5508000/panel@0";
|
|
dsi1_timing0 = "/soc@3000000/dsi1@5508000/panel@0/display-timings/timing0";
|
|
tv0 = "/soc@3000000/tcon2@5503000";
|
|
tcon2_in = "/soc@3000000/tcon2@5503000/ports/port@0";
|
|
tcon2_in_disp0 = "/soc@3000000/tcon2@5503000/ports/port@0/endpoint@0";
|
|
tcon2_in_disp1 = "/soc@3000000/tcon2@5503000/ports/port@0/endpoint@1";
|
|
tcon2_out = "/soc@3000000/tcon2@5503000/ports/port@1";
|
|
tcon2_out_hdmi = "/soc@3000000/tcon2@5503000/ports/port@1/endpoint@0";
|
|
hdmi = "/soc@3000000/hdmi@5520000";
|
|
hdmi_in = "/soc@3000000/hdmi@5520000/ports/port@0";
|
|
hdmi_in_tcon2 = "/soc@3000000/hdmi@5520000/ports/port@0/endpoint@0";
|
|
tv1 = "/soc@3000000/tcon3@5504000";
|
|
tcon3_in = "/soc@3000000/tcon3@5504000/ports/port@0";
|
|
tcon3_in_disp0 = "/soc@3000000/tcon3@5504000/ports/port@0/endpoint@0";
|
|
tcon3_in_disp1 = "/soc@3000000/tcon3@5504000/ports/port@0/endpoint@1";
|
|
tcon3_out = "/soc@3000000/tcon3@5504000/ports/port@1";
|
|
tcon3_out_edp = "/soc@3000000/tcon3@5504000/ports/port@1/endpoint@0";
|
|
drm_edp = "/soc@3000000/drm_edp@5720000";
|
|
edp_in = "/soc@3000000/drm_edp@5720000/ports/port@0";
|
|
edp_in_tcon3 = "/soc@3000000/drm_edp@5720000/ports/port@0/endpoint@0";
|
|
edp_out = "/soc@3000000/drm_edp@5720000/ports/port@1";
|
|
edp_panel_out = "/soc@3000000/drm_edp@5720000/ports/port@1/endpoint@0";
|
|
disp = "/soc@3000000/disp@5000000";
|
|
edp0 = "/soc@3000000/edp0@5720000";
|
|
lcd0 = "/soc@3000000/lcd0@1c0c000";
|
|
lcd1 = "/soc@3000000/lcd1@1c0c000";
|
|
lcd2 = "/soc@3000000/lcd2@1c0c000";
|
|
r_pio = "/soc@3000000/pinctrl@7022000";
|
|
uart8_pins_a = "/soc@3000000/pinctrl@7022000/uart8_pins@0";
|
|
uart8_pins_b = "/soc@3000000/pinctrl@7022000/uart8_pins@1";
|
|
uart9_pins_a = "/soc@3000000/pinctrl@7022000/uart9_pins@0";
|
|
uart9_pins_b = "/soc@3000000/pinctrl@7022000/uart9_pins@1";
|
|
s_twi0_pins_default = "/soc@3000000/pinctrl@7022000/s_twi0@0";
|
|
s_twi0_pins_sleep = "/soc@3000000/pinctrl@7022000/s_twi0@1";
|
|
s_irrx_pins_default = "/soc@3000000/pinctrl@7022000/s_irrx@0";
|
|
s_irrx_pins_sleep = "/soc@3000000/pinctrl@7022000/s_irrx@1";
|
|
g2d = "/soc@3000000/g2d@5440000";
|
|
pio = "/soc@3000000/pinctrl@2000000";
|
|
sdc0_pins_a = "/soc@3000000/pinctrl@2000000/sdc0@0";
|
|
sdc0_pins_b = "/soc@3000000/pinctrl@2000000/sdc0@1";
|
|
sdc0_pins_c = "/soc@3000000/pinctrl@2000000/sdc0@2";
|
|
sdc0_pins_d = "/soc@3000000/pinctrl@2000000/sdc0@3";
|
|
sdc0_pins_e = "/soc@3000000/pinctrl@2000000/sdc0@4";
|
|
sdc1_pins_a = "/soc@3000000/pinctrl@2000000/sdc1@0";
|
|
sdc1_pins_b = "/soc@3000000/pinctrl@2000000/sdc1@1";
|
|
sdc2_pins_a = "/soc@3000000/pinctrl@2000000/sdc2@0";
|
|
sdc2_pins_b = "/soc@3000000/pinctrl@2000000/sdc2@1";
|
|
sdc2_pins_c = "/soc@3000000/pinctrl@2000000/sdc2@2";
|
|
uart1_pins_a = "/soc@3000000/pinctrl@2000000/uart1@0";
|
|
uart1_pins_b = "/soc@3000000/pinctrl@2000000/uart1@1";
|
|
dsi0_4lane_pins_a = "/soc@3000000/pinctrl@2000000/dsi0_4lane@0";
|
|
dsi0_4lane_pins_b = "/soc@3000000/pinctrl@2000000/dsi0_4lane@1";
|
|
dsi1_4lane_pins_a = "/soc@3000000/pinctrl@2000000/dsi1_4lane@0";
|
|
dsi1_4lane_pins_b = "/soc@3000000/pinctrl@2000000/dsi1_4lane@1";
|
|
rgb18_pins_a = "/soc@3000000/pinctrl@2000000/rgb18@0";
|
|
rgb18_pins_b = "/soc@3000000/pinctrl@2000000/rgb18@1";
|
|
lvds0_pins_a = "/soc@3000000/pinctrl@2000000/lvds0@0";
|
|
lvds0_pins_b = "/soc@3000000/pinctrl@2000000/lvds0@1";
|
|
lvds1_pins_a = "/soc@3000000/pinctrl@2000000/lvds1@0";
|
|
lvds1_pins_b = "/soc@3000000/pinctrl@2000000/lvds1@1";
|
|
lvds2_pins_a = "/soc@3000000/pinctrl@2000000/lvds2@0";
|
|
lvds2_pins_b = "/soc@3000000/pinctrl@2000000/lvds2@1";
|
|
lvds3_pins_a = "/soc@3000000/pinctrl@2000000/lvds3@0";
|
|
lvds3_pins_b = "/soc@3000000/pinctrl@2000000/lvds3@1";
|
|
rgb1_24pins_a = "/soc@3000000/pinctrl@2000000/rgb1@0";
|
|
rgb1_24pins_b = "/soc@3000000/pinctrl@2000000/rgb1@1";
|
|
rgb0_24pins_a = "/soc@3000000/pinctrl@2000000/rgb0@0";
|
|
rgb0_24pins_b = "/soc@3000000/pinctrl@2000000/rgb0@1";
|
|
rgb0_18pins_a = "/soc@3000000/pinctrl@2000000/rgb0@2";
|
|
rgb0_18pins_b = "/soc@3000000/pinctrl@2000000/rgb0@3";
|
|
csi_mclk0_pins_a = "/soc@3000000/pinctrl@2000000/csi_mclk0@0";
|
|
csi_mclk0_pins_b = "/soc@3000000/pinctrl@2000000/csi_mclk0@1";
|
|
csi_mclk1_pins_a = "/soc@3000000/pinctrl@2000000/csi_mclk1@0";
|
|
csi_mclk1_pins_b = "/soc@3000000/pinctrl@2000000/csi_mclk1@1";
|
|
csi_mclk2_pins_a = "/soc@3000000/pinctrl@2000000/csi_mclk2@0";
|
|
csi_mclk2_pins_b = "/soc@3000000/pinctrl@2000000/csi_mclk2@1";
|
|
csi_mclk3_pins_a = "/soc@3000000/pinctrl@2000000/csi_mclk3@0";
|
|
csi_mclk3_pins_b = "/soc@3000000/pinctrl@2000000/csi_mclk3@1";
|
|
ncsi_bt656_pins_a = "/soc@3000000/pinctrl@2000000/ncsi_BT656@0";
|
|
ncsi_bt656_pins_b = "/soc@3000000/pinctrl@2000000/ncsi_BT656@1";
|
|
ncsi_bt1120_pins_a = "/soc@3000000/pinctrl@2000000/ncsi_BT1120@0";
|
|
ncsi_bt1120_pins_b = "/soc@3000000/pinctrl@2000000/ncsi_BT1120@1";
|
|
mipia_pins_a = "/soc@3000000/pinctrl@2000000/mipia@0";
|
|
mipia_pins_b = "/soc@3000000/pinctrl@2000000/mipia@1";
|
|
mipib_pins_a = "/soc@3000000/pinctrl@2000000/mipib@0";
|
|
mipib_pins_b = "/soc@3000000/pinctrl@2000000/mipib@1";
|
|
mipib_4lane_pins_a = "/soc@3000000/pinctrl@2000000/mipib_4lane@0";
|
|
mipib_4lane_pins_b = "/soc@3000000/pinctrl@2000000/mipib_4lane@1";
|
|
mipic_pins_a = "/soc@3000000/pinctrl@2000000/mipic@0";
|
|
mipic_pins_b = "/soc@3000000/pinctrl@2000000/mipic@1";
|
|
mipid_pins_a = "/soc@3000000/pinctrl@2000000/mipid@0";
|
|
mipid_pins_b = "/soc@3000000/pinctrl@2000000/mipid@1";
|
|
mipid_4lane_pins_a = "/soc@3000000/pinctrl@2000000/mipid_4lane@0";
|
|
mipid_4lane_pins_b = "/soc@3000000/pinctrl@2000000/mipid_4lane@1";
|
|
test_pins_a = "/soc@3000000/pinctrl@2000000/test_pins@0";
|
|
test_pins_b = "/soc@3000000/pinctrl@2000000/test_pins@1";
|
|
uart0_pins_a = "/soc@3000000/pinctrl@2000000/uart0_pins@0";
|
|
uart0_pins_b = "/soc@3000000/pinctrl@2000000/uart0_pins@1";
|
|
uart2_pins_a = "/soc@3000000/pinctrl@2000000/uart2_pins@0";
|
|
uart2_pins_b = "/soc@3000000/pinctrl@2000000/uart2_pins@1";
|
|
uart3_pins_a = "/soc@3000000/pinctrl@2000000/uart3_pins@0";
|
|
uart3_pins_b = "/soc@3000000/pinctrl@2000000/uart3_pins@1";
|
|
uart4_pins_a = "/soc@3000000/pinctrl@2000000/uart4_pins@0";
|
|
uart4_pins_b = "/soc@3000000/pinctrl@2000000/uart4_pins@1";
|
|
uart5_pins_a = "/soc@3000000/pinctrl@2000000/uart5_pins@0";
|
|
uart5_pins_b = "/soc@3000000/pinctrl@2000000/uart5_pins@1";
|
|
uart6_pins_a = "/soc@3000000/pinctrl@2000000/uart6_pins@0";
|
|
uart6_pins_b = "/soc@3000000/pinctrl@2000000/uart6_pins@1";
|
|
uart7_pins_a = "/soc@3000000/pinctrl@2000000/uart7_pins@0";
|
|
uart7_pins_b = "/soc@3000000/pinctrl@2000000/uart7_pins@1";
|
|
pwm0_0_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_0@0";
|
|
pwm0_0_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_0@1";
|
|
pwm0_1_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_1@0";
|
|
pwm0_1_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_1@1";
|
|
pwm0_2_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_2@0";
|
|
pwm0_2_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_2@1";
|
|
pwm0_3_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_3@0";
|
|
pwm0_3_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_3@1";
|
|
pwm0_4_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_4@0";
|
|
pwm0_4_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_4@1";
|
|
pwm0_5_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_5@0";
|
|
pwm0_5_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_5@1";
|
|
pwm0_6_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_6@0";
|
|
pwm0_6_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_6@1";
|
|
pwm0_7_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_7@0";
|
|
pwm0_7_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_7@1";
|
|
pwm0_8_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_8@0";
|
|
pwm0_8_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_8@1";
|
|
pwm0_9_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_9@0";
|
|
pwm0_9_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_9@1";
|
|
pwm0_10_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_10@0";
|
|
pwm0_10_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_10@1";
|
|
pwm0_11_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_11@0";
|
|
pwm0_11_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_11@1";
|
|
pwm0_12_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_12@0";
|
|
pwm0_12_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_12@1";
|
|
pwm0_13_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_13@0";
|
|
pwm0_13_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_13@1";
|
|
pwm0_14_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_14@0";
|
|
pwm0_14_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_14@1";
|
|
pwm0_15_pin_active = "/soc@3000000/pinctrl@2000000/pwm0_15@0";
|
|
pwm0_15_pin_sleep = "/soc@3000000/pinctrl@2000000/pwm0_15@1";
|
|
ledc_pins_a = "/soc@3000000/pinctrl@2000000/ledc@0";
|
|
ledc_pins_b = "/soc@3000000/pinctrl@2000000/ledc@1";
|
|
irrx_pins_default = "/soc@3000000/pinctrl@2000000/irrx@0";
|
|
irrx_pins_sleep = "/soc@3000000/pinctrl@2000000/irrx@1";
|
|
irtx_pins_default = "/soc@3000000/pinctrl@2000000/irtx@0";
|
|
irtx_pins_sleep = "/soc@3000000/pinctrl@2000000/irtx@1";
|
|
twi0_pins_default = "/soc@3000000/pinctrl@2000000/twi0@0";
|
|
twi0_pins_sleep = "/soc@3000000/pinctrl@2000000/twi0@1";
|
|
twi1_pins_default = "/soc@3000000/pinctrl@2000000/twi1@0";
|
|
twi1_pins_sleep = "/soc@3000000/pinctrl@2000000/twi1@1";
|
|
twi3_pins_default = "/soc@3000000/pinctrl@2000000/twi3@0";
|
|
twi3_pins_sleep = "/soc@3000000/pinctrl@2000000/twi3@1";
|
|
twi4_pins_default = "/soc@3000000/pinctrl@2000000/twi4@0";
|
|
twi4_pins_sleep = "/soc@3000000/pinctrl@2000000/twi4@1";
|
|
twi5_pins_default = "/soc@3000000/pinctrl@2000000/twi5@0";
|
|
twi5_pins_sleep = "/soc@3000000/pinctrl@2000000/twi5@1";
|
|
rgb24_pins_a = "/soc@3000000/pinctrl@2000000/rgb24@0";
|
|
rgb24_pins_b = "/soc@3000000/pinctrl@2000000/rgb24@1";
|
|
ncsi_pins_a = "/soc@3000000/pinctrl@2000000/ncsi@0";
|
|
ncsi_pins_b = "/soc@3000000/pinctrl@2000000/ncsi@1";
|
|
i2s1_pins_a = "/soc@3000000/pinctrl@2000000/i2s1@0";
|
|
i2s1_pins_b = "/soc@3000000/pinctrl@2000000/i2s1@1";
|
|
i2s1_pins_c = "/soc@3000000/pinctrl@2000000/i2s1@2";
|
|
i2s1_pins_d = "/soc@3000000/pinctrl@2000000/i2s1@3";
|
|
owa_pins_a = "/soc@3000000/pinctrl@2000000/owa@0";
|
|
owa_pins_b = "/soc@3000000/pinctrl@2000000/owa@1";
|
|
nand0_pins_default = "/soc@3000000/pinctrl@2000000/nand0@0";
|
|
nand0_pins_rb = "/soc@3000000/pinctrl@2000000/nand0@1";
|
|
nand0_pins_sleep = "/soc@3000000/pinctrl@2000000/nand0@2";
|
|
i2s0_pins_a = "/soc@3000000/pinctrl@2000000/i2s0@0";
|
|
i2s0_pins_b = "/soc@3000000/pinctrl@2000000/i2s0@1";
|
|
i2s0_pins_c = "/soc@3000000/pinctrl@2000000/i2s0@2";
|
|
i2s0_pins_d = "/soc@3000000/pinctrl@2000000/i2s0@3";
|
|
gmac1_pins_default = "/soc@3000000/pinctrl@2000000/gmac1@0";
|
|
gmac1_pins_sleep = "/soc@3000000/pinctrl@2000000/gmac1@1";
|
|
spi1_pin_default = "/soc@3000000/pinctrl@2000000/spi1_pin_default";
|
|
spi1_pin_sleep = "/soc@3000000/pinctrl@2000000/spi1_pin_sleep";
|
|
spi2_pin_default = "/soc@3000000/pinctrl@2000000/spi2_pin_default";
|
|
spi2_pin_sleep = "/soc@3000000/pinctrl@2000000/spi2_pin_sleep";
|
|
pinctrl_test = "/soc@3000000/pinctrl_test@2000000";
|
|
ths0 = "/soc@3000000/ths0@200a000";
|
|
ths1 = "/soc@3000000/ths0@2009400";
|
|
soc_timer0 = "/soc@3000000/timer@3008000";
|
|
dump_reg = "/soc@3000000/dump_reg@40000";
|
|
soft_jtag_master = "/soc@3000000/soft_jtag_master@0";
|
|
reg_pio1_8 = "/soc@3000000/pio-18";
|
|
reg_pio2_8 = "/soc@3000000/pio-28";
|
|
reg_pio3_3 = "/soc@3000000/pio-33";
|
|
uart0 = "/soc@3000000/uart@2500000";
|
|
uart1 = "/soc@3000000/uart@2500400";
|
|
uart2 = "/soc@3000000/uart@2500800";
|
|
uart3 = "/soc@3000000/uart@2500c00";
|
|
uart4 = "/soc@3000000/uart@2501000";
|
|
uart5 = "/soc@3000000/uart@2501400";
|
|
uart6 = "/soc@3000000/uart@2501800";
|
|
uart7 = "/soc@3000000/uart@2501c00";
|
|
uart8 = "/soc@3000000/uart@7080000";
|
|
uart9 = "/soc@3000000/uart@7080400";
|
|
dma = "/soc@3000000/dma-controller@3002000";
|
|
dma1 = "/soc@3000000/dma1-controller@7121000";
|
|
npu = "/soc@3000000/npu@7122000";
|
|
npu_opp_table = "/soc@3000000/npu-opp-table";
|
|
npu_opp_table_546 = "/soc@3000000/npu-opp-table/opp-546";
|
|
npu_opp_table_696 = "/soc@3000000/npu-opp-table/opp-696";
|
|
wdt = "/soc@3000000/watchdog@2050000";
|
|
gpadc0 = "/soc@3000000/gpadc0@2009000";
|
|
gpadc1 = "/soc@3000000/gpadc1@2009c00";
|
|
dsp0_rproc = "/soc@3000000/dsp0_rproc@0";
|
|
e906_rproc = "/soc@3000000/e906_rproc@7130000";
|
|
msgbox = "/soc@3000000/msgbox@3003000";
|
|
hwspinlock = "/soc@3000000/hwspinlock@3005000";
|
|
pwm0 = "/soc@3000000/pwm0@2000c00";
|
|
pwm0_0 = "/soc@3000000/pwm0_0@2000c10";
|
|
pwm0_1 = "/soc@3000000/pwm0_1@2000c11";
|
|
pwm0_2 = "/soc@3000000/pwm0_2@2000c12";
|
|
pwm0_3 = "/soc@3000000/pwm0_3@2000c13";
|
|
pwm0_4 = "/soc@3000000/pwm0_4@2000c14";
|
|
pwm0_5 = "/soc@3000000/pwm0_5@2000c15";
|
|
pwm0_6 = "/soc@3000000/pwm0_6@2000c16";
|
|
pwm0_7 = "/soc@3000000/pwm0_7@2000c17";
|
|
pwm0_8 = "/soc@3000000/pwm0_8@2000c18";
|
|
pwm0_9 = "/soc@3000000/pwm0_9@2000c19";
|
|
pwm0_10 = "/soc@3000000/pwm0_10@2000c1a";
|
|
pwm0_11 = "/soc@3000000/pwm0_11@2000c1b";
|
|
pwm0_12 = "/soc@3000000/pwm0_12@2000c1c";
|
|
pwm0_13 = "/soc@3000000/pwm0_13@2000c1d";
|
|
pwm0_14 = "/soc@3000000/pwm0_14@2000c1e";
|
|
pwm0_15 = "/soc@3000000/pwm0_15@2000c1f";
|
|
pwm1 = "/soc@3000000/pwm1@2051000";
|
|
pwm1_0 = "/soc@3000000/pwm1_0@2051010";
|
|
pwm1_1 = "/soc@3000000/pwm1_1@2051011";
|
|
pwm1_2 = "/soc@3000000/pwm1_2@2051012";
|
|
pwm1_3 = "/soc@3000000/pwm1_3@2051013";
|
|
s_pwm0 = "/soc@3000000/s_pwm0@7020c00";
|
|
s_pwm0_0 = "/soc@3000000/s_pwm0_0@7020c10";
|
|
s_pwm0_1 = "/soc@3000000/s_pwm0_1@7020c11";
|
|
mcu_pwm0 = "/soc@3000000/mcu_pwm0@7103000";
|
|
mcu_pwm0_0 = "/soc@3000000/mcu_pwm0_0@7103010";
|
|
mcu_pwm0_1 = "/soc@3000000/mcu_pwm0_1@7103020";
|
|
mcu_pwm0_2 = "/soc@3000000/mcu_pwm0_2@7103030";
|
|
mcu_pwm0_3 = "/soc@3000000/mcu_pwm0_3@7103040";
|
|
mcu_pwm0_4 = "/soc@3000000/mcu_pwm0_4@7103050";
|
|
mcu_pwm0_5 = "/soc@3000000/mcu_pwm0_5@7103060";
|
|
mcu_pwm0_6 = "/soc@3000000/mcu_pwm0_6@7103070";
|
|
mcu_pwm0_7 = "/soc@3000000/mcu_pwm0_7@7103080";
|
|
ledc = "/soc@3000000/ledc@2008000";
|
|
irrx = "/soc@3000000/irrx@2005000";
|
|
s_irrx = "/soc@3000000/s_irrx@7040000";
|
|
irtx = "/soc@3000000/irtx@2003000";
|
|
twi0 = "/soc@3000000/twi0@2502000";
|
|
twi1 = "/soc@3000000/twi1@2502400";
|
|
twi2 = "/soc@3000000/twi2@2502800";
|
|
twi3 = "/soc@3000000/twi3@2502c00";
|
|
ctp = "/soc@3000000/twi3@2502c00/ctp@0";
|
|
twi4 = "/soc@3000000/twi4@2503000";
|
|
twi5 = "/soc@3000000/twi5@2503400";
|
|
twi6 = "/soc@3000000/s_twi0@7081400";
|
|
axp1530 = "/soc@3000000/s_twi0@7081400/axp1530@36";
|
|
reg_ext_axp1530_dcdc1 = "/soc@3000000/s_twi0@7081400/axp1530@36/regulators/dcdc1";
|
|
reg_ext_axp1530_dcdc2 = "/soc@3000000/s_twi0@7081400/axp1530@36/regulators/dcdc2";
|
|
reg_ext_axp1530_dcdc3 = "/soc@3000000/s_twi0@7081400/axp1530@36/regulators/dcdc3";
|
|
reg_ext_axp1530_aldo1 = "/soc@3000000/s_twi0@7081400/axp1530@36/regulators/ldo1";
|
|
reg_ext_axp1530_dldo1 = "/soc@3000000/s_twi0@7081400/axp1530@36/regulators/ldo2";
|
|
pmu0 = "/soc@3000000/s_twi0@7081400/pmu@35";
|
|
usb_power_supply = "/soc@3000000/s_twi0@7081400/pmu@35/usb_power_supply";
|
|
gpio_power_supply = "/soc@3000000/s_twi0@7081400/pmu@35/gpio_power_supply";
|
|
bat_power_supply = "/soc@3000000/s_twi0@7081400/pmu@35/bat-power-supply";
|
|
powerkey0 = "/soc@3000000/s_twi0@7081400/pmu@35/powerkey@0";
|
|
regulator0 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0";
|
|
reg_dcdc1 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/dcdc1";
|
|
reg_dcdc2 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/dcdc2";
|
|
reg_dcdc3 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/dcdc3";
|
|
reg_dcdc4 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/dcdc4";
|
|
reg_rtcldo = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/rtcldo";
|
|
reg_aldo1 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/aldo1";
|
|
reg_aldo2 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/aldo2";
|
|
reg_aldo3 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/aldo3";
|
|
reg_aldo4 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/aldo4";
|
|
reg_bldo1 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/bldo1";
|
|
reg_bldo2 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/bldo2";
|
|
reg_bldo3 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/bldo3";
|
|
reg_bldo4 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/bldo4";
|
|
reg_cldo1 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/cldo1";
|
|
reg_cldo2 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/cldo2";
|
|
reg_cldo3 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/cldo3";
|
|
reg_cldo4 = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/cldo4";
|
|
reg_cpusldo = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/cpusldo";
|
|
reg_vmid = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/vmid";
|
|
reg_drivevbus = "/soc@3000000/s_twi0@7081400/pmu@35/regulators@0/drivevbus";
|
|
axp_gpio0 = "/soc@3000000/s_twi0@7081400/pmu@35/axp_gpio@0";
|
|
twi7 = "/soc@3000000/s_twi1@7081800";
|
|
twi8 = "/soc@3000000/s_twi2@7081c00";
|
|
spi0 = "/soc@3000000/spi@4025000";
|
|
spi1 = "/soc@3000000/spi@4026000";
|
|
spi2 = "/soc@3000000/spi@4027000";
|
|
r_spi0 = "/soc@3000000/spi@7092000";
|
|
spif0 = "/soc@3000000/spif@47f0000";
|
|
nand0 = "/soc@3000000/nand0@4011000";
|
|
lradc = "/soc@3000000/lradc@2009800";
|
|
nsi0 = "/soc@3000000/nsi-controller@2020000";
|
|
npd0 = "/soc@3000000/npd@2070000";
|
|
cryptoengine = "/soc@3000000/ce@3040000";
|
|
rtc = "/soc@3000000/rtc@7090000";
|
|
sdc2 = "/soc@3000000/sdmmc@4022000";
|
|
sdc0 = "/soc@3000000/sdmmc@4020000";
|
|
sdc1 = "/soc@3000000/sdmmc@4021000";
|
|
usbc0 = "/soc@3000000/usbc0@10";
|
|
udc = "/soc@3000000/udc-controller@4100000";
|
|
ehci0 = "/soc@3000000/ehci0-controller@4101000";
|
|
ohci0 = "/soc@3000000/ohci0-controller@4101400";
|
|
usbc1 = "/soc@3000000/usbc1@11";
|
|
ehci1 = "/soc@3000000/ehci1-controller@4200000";
|
|
ohci1 = "/soc@3000000/ohci1-controller@4200400";
|
|
usbc2 = "/soc@3000000/usbc2@12";
|
|
xhci2 = "/soc@3000000/usbc2@12/xhci2-controller@4d00000";
|
|
u2phy = "/soc@3000000/phy@4e00000";
|
|
vind0 = "/soc@3000000/vind@5800800";
|
|
csi0 = "/soc@3000000/vind@5800800/csi@5820000";
|
|
csi1 = "/soc@3000000/vind@5800800/csi@5821000";
|
|
csi2 = "/soc@3000000/vind@5800800/csi@5822000";
|
|
csi3 = "/soc@3000000/vind@5800800/csi@5823000";
|
|
mipi0 = "/soc@3000000/vind@5800800/mipi@5810100";
|
|
mipi1 = "/soc@3000000/vind@5800800/mipi@5810200";
|
|
mipi2 = "/soc@3000000/vind@5800800/mipi@5810300";
|
|
mipi3 = "/soc@3000000/vind@5800800/mipi@5810400";
|
|
tdm0 = "/soc@3000000/vind@5800800/tdm@5908000";
|
|
isp00 = "/soc@3000000/vind@5800800/isp@5900000";
|
|
isp01 = "/soc@3000000/vind@5800800/isp@58ffffc";
|
|
isp02 = "/soc@3000000/vind@5800800/isp@58ffff8";
|
|
isp03 = "/soc@3000000/vind@5800800/isp@58ffff4";
|
|
isp10 = "/soc@3000000/vind@5800800/isp@4";
|
|
isp20 = "/soc@3000000/vind@5800800/isp@5";
|
|
isp30 = "/soc@3000000/vind@5800800/isp@6";
|
|
scaler00 = "/soc@3000000/vind@5800800/scaler@5910000";
|
|
scaler01 = "/soc@3000000/vind@5800800/scaler@590fffc";
|
|
scaler02 = "/soc@3000000/vind@5800800/scaler@590fff8";
|
|
scaler03 = "/soc@3000000/vind@5800800/scaler@590fff4";
|
|
scaler10 = "/soc@3000000/vind@5800800/scaler@5910400";
|
|
scaler11 = "/soc@3000000/vind@5800800/scaler@59103fc";
|
|
scaler12 = "/soc@3000000/vind@5800800/scaler@59103f8";
|
|
scaler13 = "/soc@3000000/vind@5800800/scaler@59103f4";
|
|
scaler20 = "/soc@3000000/vind@5800800/scaler@5910800";
|
|
scaler21 = "/soc@3000000/vind@5800800/scaler@59107fc";
|
|
scaler22 = "/soc@3000000/vind@5800800/scaler@59107f8";
|
|
scaler23 = "/soc@3000000/vind@5800800/scaler@59107f4";
|
|
scaler30 = "/soc@3000000/vind@5800800/scaler@5910c00";
|
|
scaler31 = "/soc@3000000/vind@5800800/scaler@5910bfc";
|
|
scaler32 = "/soc@3000000/vind@5800800/scaler@5910bf8";
|
|
scaler33 = "/soc@3000000/vind@5800800/scaler@5910bf4";
|
|
scaler40 = "/soc@3000000/vind@5800800/scaler@16";
|
|
scaler50 = "/soc@3000000/vind@5800800/scaler@17";
|
|
actuator0 = "/soc@3000000/vind@5800800/actuator@2108180";
|
|
flash0 = "/soc@3000000/vind@5800800/flash@2108190";
|
|
sensor0 = "/soc@3000000/vind@5800800/sensor@5812000";
|
|
sensor1 = "/soc@3000000/vind@5800800/sensor@5812010";
|
|
sensor2 = "/soc@3000000/vind@5800800/sensor@5812020";
|
|
sensor3 = "/soc@3000000/vind@5800800/sensor@5812030";
|
|
sensor_list0 = "/soc@3000000/vind@5800800/sensor_list@5812040";
|
|
sensor_list1 = "/soc@3000000/vind@5800800/sensor_list@5812050";
|
|
vinc00 = "/soc@3000000/vind@5800800/vinc@5830000";
|
|
vinc01 = "/soc@3000000/vind@5800800/vinc@582fffc";
|
|
vinc02 = "/soc@3000000/vind@5800800/vinc@582fff8";
|
|
vinc03 = "/soc@3000000/vind@5800800/vinc@582fff4";
|
|
vinc10 = "/soc@3000000/vind@5800800/vinc@5831000";
|
|
vinc11 = "/soc@3000000/vind@5800800/vinc@5830ffc";
|
|
vinc12 = "/soc@3000000/vind@5800800/vinc@5830ff8";
|
|
vinc13 = "/soc@3000000/vind@5800800/vinc@5830ff4";
|
|
vinc20 = "/soc@3000000/vind@5800800/vinc@5832000";
|
|
vinc21 = "/soc@3000000/vind@5800800/vinc@5831ffc";
|
|
vinc22 = "/soc@3000000/vind@5800800/vinc@5831ff8";
|
|
vinc23 = "/soc@3000000/vind@5800800/vinc@5831ff4";
|
|
vinc30 = "/soc@3000000/vind@5800800/vinc@5833000";
|
|
vinc31 = "/soc@3000000/vind@5800800/vinc@5832ffc";
|
|
vinc32 = "/soc@3000000/vind@5800800/vinc@5832ff8";
|
|
vinc33 = "/soc@3000000/vind@5800800/vinc@5832ff4";
|
|
vinc40 = "/soc@3000000/vind@5800800/vinc@5834000";
|
|
vinc50 = "/soc@3000000/vind@5800800/vinc@5835000";
|
|
di = "/soc@3000000/deinterlace@5400000";
|
|
gpu = "/soc@3000000/gpu@1800000";
|
|
ipa_dvfs = "/soc@3000000/gpu@1800000/ipa_dvfs";
|
|
gpu_opp_table = "/soc@3000000/gpu-opp-table";
|
|
combophy = "/soc@3000000/phy@4f00000";
|
|
pcie = "/soc@3000000/pcie@4800000";
|
|
codec = "/soc@3000000/codec@7110000";
|
|
codec_plat = "/soc@3000000/codec_plat";
|
|
codec_mach = "/soc@3000000/codec_mach";
|
|
hdmi_codec = "/soc@3000000/hdmi_codec";
|
|
edp_codec = "/soc@3000000/edp_codec";
|
|
owa_plat = "/soc@3000000/owa_plat@7116000";
|
|
owa_mach = "/soc@3000000/owa_mach";
|
|
dmic_plat = "/soc@3000000/dmic_plat@7111000";
|
|
dmic_mach = "/soc@3000000/dmic_mach";
|
|
i2s0_plat = "/soc@3000000/i2s0_plat@7112000";
|
|
i2s0_mach = "/soc@3000000/i2s0_mach";
|
|
i2s1_plat = "/soc@3000000/i2s1_plat@7113000";
|
|
i2s1_mach = "/soc@3000000/i2s1_mach";
|
|
i2s1_cpu = "/soc@3000000/i2s1_mach/soundcard-mach,cpu";
|
|
i2s1_codec = "/soc@3000000/i2s1_mach/soundcard-mach,codec";
|
|
i2s2_plat = "/soc@3000000/i2s2_plat@7114000";
|
|
i2s2_mach = "/soc@3000000/i2s2_mach";
|
|
i2s2_cpu = "/soc@3000000/i2s2_mach/soundcard-mach,cpu";
|
|
i2s2_codec = "/soc@3000000/i2s2_mach/soundcard-mach,codec";
|
|
i2s3_plat = "/soc@3000000/i2s3_plat@7115000";
|
|
i2s3_mach = "/soc@3000000/i2s3_mach";
|
|
i2s3_cpu = "/soc@3000000/i2s3_mach/soundcard-mach,cpu";
|
|
i2s3_codec = "/soc@3000000/i2s3_mach/soundcard-mach,codec";
|
|
rfkill = "/soc@3000000/rfkill";
|
|
addr_mgt = "/soc@3000000/addr_mgt";
|
|
btlpm = "/soc@3000000/btlpm";
|
|
mdio0 = "/soc@3000000/mdio0@4500048";
|
|
gmac0_phy0 = "/soc@3000000/mdio0@4500048/ethernet-phy@1";
|
|
gmac0 = "/soc@3000000/gmac0@4500000";
|
|
gmac1 = "/soc@3000000/ethernet@4510000";
|
|
gmac1_stmmac_axi_setup = "/soc@3000000/ethernet@4510000/stmmac-axi-config";
|
|
gmac1_mtl_rx_setup = "/soc@3000000/ethernet@4510000/rx-queues-config";
|
|
gmac1_mtl_tx_setup = "/soc@3000000/ethernet@4510000/tx_queues-config";
|
|
mdio1 = "/soc@3000000/ethernet@4510000/mdio1@1";
|
|
gmac1_phy0 = "/soc@3000000/ethernet@4510000/mdio1@1/ethernet-phy@1";
|
|
sram_ctrl = "/soc@3000000/sram_ctrl@3000000";
|
|
leds = "/gpio-leds";
|
|
ap6256_wifi = "/ap6256_wifi";
|
|
reg_exxt_vbus = "/exxt-vbus";
|
|
reg_usb0_vbus = "/usb0-vbus";
|
|
reg_usb1_vbus = "/usb1-vbus";
|
|
standby_param = "/standby_param";
|
|
arisc_config = "/arisc_config";
|
|
edp_panel = "/edp_panel";
|
|
panel_in = "/edp_panel/ports/port@0";
|
|
edp_panel_in = "/edp_panel/ports/port@0/endpoint@0";
|
|
edp_panel_backlight = "/edp-panel-backlight";
|
|
backlight0 = "/backlight0";
|
|
axp2202_parameter = "/axp2202-parameter";
|
|
};
|
|
};
|